Pulse discriminator

Claim 2

A pulse discriminator having an input and a pair of outputs for identifying a sequence of signals, the polarities of which may vary, particularly for an automatic telegraph exchange, receiving signals transmitted at different modulation rates comprising: first means for receiving at said input said signals to be identified; second means for detecting the polarity of said received signals; third means responsive to said first and second means for storing the polarity of those received signals having a first predetermined polarity; and fourth means responsive to said third means and said second means for delivering a signal to one of said outputs only after said first predetermined polarity has been stored a first specified period of time.

Claim 3

A pulse discriminator according to claim 1, further including fifth means responsive to said second means for storing the polarity of those received signals having a second predetermined polarity; and sixth means response to said second means and said fifth means for delivering an output signal to both outputs of said pair of outputs only after said second predetermined polarity has been stored a second specified period of time.

Claim 4

A pulse discriminator according to claim 2, wherein said second means comprises a first delay circuit for preventing the storage of the polarity of said received signals until said first predetermined polarity has been continuously detected over a minimum time duration.

Claim 5

A pulse discriminator according to claim 3, wherein said fourth means includes a time base control circuit responsive to said third means for preventing the delivery of a signal to said one of said outputs for said first specified period of time after said third means has begun storing said first predetermined polarity.

Claim 6

A pulse discriminator according to claim 4, wherein said third means comprises a first flip-flop having one of its inputs connected to said first means and the other input connected to said second means, while having its outputs connected to said fifth means, and further having one of its outputs connected to said time base control circuit.

Claim 7

A pulse discriminator according to claim 5, wherein said time base control circuit includes a first transistor circuit coupled to said one of the outputs of said first flip-flop through a second delay circuit and further includes a second transistor circuit connected to and controlled by said first transistor circuit, whereby, upon the storage of said first predetermined polarity by said flip-flop, said first transistor will be cut off, thereby causing said second transistor to conduct, so as to provide an output inhibiting signal and, thus, prevent the delivery of a signal to one of said outputs until after said first predetermined period of time controlled by said second delay circuit.

Claim 8

A pulse discriminator according to claim 6, wherein said second means further includes a first biasing transistor circuit, the input of which is connected to said first delay circuit and the output of which is connected to said fourth means and said third means, whereby, upon the continuous detection of said first predetermined polarity over said minimum time duration, said first biasing transistor will deliver a trigger voltage to said third means and said fourth means.

Claim 9

A pulse discriminator according to claim 7, wherein said fourth means further includes an output control circuit comprising a first output transistor, one electrode of which is connected to one of said outputs, while another electrode of which is coupled to said second transistor of said time base control circuit and to the first biasing transistor of said second means, whereby, upon the elapse of said first specified period of time, said inhibiting signal will be withdrawn from said first output transistor and said trigger voltage will, thereby, bias said first output transistor, so as to deliver an output signal to said one of said outputs.

Claim 10

A pulse discriminator according to claim 8, wherein said fifth means comprises a second flip-flop having one of its inputs connected to both said first and third means, and the other of its inputs connected to both said second and third means, while having its outputs connected to said output control circuit and, further, having one of its inputs connected to said sixth means.

Claim 11

A pulse discriminator according to claim 9. wherein said sixth means comprises a negative pulse counting circuit, the input of which is connected to said one of said outputs of said second flip-flop through a third delay circuit and the output of which is connected to said other of the inputs of said second flip-flop, whereby said second flip-flop is prevented from delivering an output signal to both outputs of said pair of outputs until said second flip-flop has stored said second predetermined polarity for said second specified period of time.

Claim 12

A pulse discriminator according to claim 10, whereby said output control circuit further comprises a second output transistor, one electrode of which is connected to said pair of outputs, while another electrode of which is coupled to one of the outputs of said second flip-flop and to said second transistor of said time base control circuit, whereby, upon the elapse of said second specified period of time, said trigger voltage will be delivered to said second output transistor and, thereby, said second output transistor will deliver an output signal to said pair of outputs.

Claim 13

A pulse discriminator having an input and a pair of outputs for identifying a sequence of signals, the polarities of which may vary, particularly for an automatic telegraph exchange, receiving signals transmitted at different modulation rates comprising: first means for receiving at said input said signals to be identified; second means responsive to said first means for detecting the polarity of said received signals; and third means responsive to said second means and said first means for delivering a signal to a first of said outputs in response to a first predetermined polarity of said received signals, further including fourth means, responsive to said second means and said first means, for delivering a signal to a second of said pair of outputs in response to a second predetermined polarity of said received signals and, a first holding means, responsive to said second means and said fourth means, for maintaining the delivery of a signal to said first of said outputs upon the cessation of the detection of a signal having said first predetermined polarity and the subsequent detection of a signal having said second predetermined polarity by said second means.

Claim 14

A pulse discriminator having an input and a pair of outputs for identifying a sequence of signals, the polarities of which may vary, particularly for an automatic telegraph exchange, receiving signals transmitted at different modulation rates comprising: first means for receiving at said input said signals to be identified; second means responsive to said first means for detecting the polarity of said received signals; and third means responsive to said second means and said first means for delivering a signal to a first of said outputs in response to a first predetermined polarity of said received signals, further including fourth means, responsive to said second means and said first means, for delivering a signal to a second of said pair of outputs in response to a second predetermined polarity of said received signals and, a first holding means, responsive to said second means and said fourth means, for maintaining the delivery of a signal to said first of said outputs upon the cessation of the detection of a signal having said first predetermined polarity and the subsequent detection of a signal having said second predetermined polarity by said second means.

Claim 15

A pulse discriminator according to claim 12, further including a second holding means for maintaining the delivery of a signal to said second of said outputs upon the cessation of the detection of a signal having said second predetermined polarity and the subsequent detection of a signal having said first predetermined polarity by said second means.

Claim 16

A pulse discriminator according to claim 12, wherein said third means concludes a first transistor circuit connected to said second means for preventing the delivery of a signal to said second of said pair of outputs by said fourth means.

Claim 17

A pulse discriminator according to cLaim 14, wherein said second means comprises a pair of diodes connected to said first means, one of said diodes being connected to pass received signals having a first predetermined polarity and the other of said diodes being connected to pass received signals having a second predetermined polarity.

Claim 18

A pulse discriminator according to claim 15, wherein one side of said first transistor circuit is connected to said second diode and another side of said first transistor circuit is switchably connected to an energizing source for controlling the operation of said first transistor circuit in response to the detection of a signal having said first predetermined polarity by said second means.

Claim 19

A pulse discriminator according to claim 16, wherein said fourth means includes a second transistor circuit connected to said second diode and to said first transistor circuit for delivering a signal to said first holding circuit in response to the detection by said second means of a signal having said second predetermined polarity, whereby said first holding circuit will maintain the delivery of a signal to said first output of said pair of outputs.

Claim 20

A pulse discriminator according to claim 17, wherein said first holding circuit comprises a third transistor circuit responsive to the operation of said second transistor circuit, whereby upon the cessation of a signal having said first predetermined polarity and the subsequent detection of a signal having said second predetermined polarity, by said second means, said second transistor circuit will conduct, thereby, causing said third transistor circuit to conduct so as to maintain the delivery of an output signal to said first output.

Claim 21

A pulse discriminator according to claim 18, wherein said first output comprises a call relay circuit.

Claim 22

A pulse discriminator according to claim 18, wherein said second output comprises a self locking rapid call relay.