Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric

Claim 1

A method for retarding the corrosion of metallization lines in an integrated circuit comprising a silicon substrate having a passivation layer of silicon dioxide on the upper surface thereof, circuit elements located on the surface of the passivation layer, and multiple metallization lines placed on the substrate and are vertically spaced apart from each other by polyimide insulating layers which method comprises the steps of: (a) placing first metallization line(s) onto the surface of the passivation layer so as to connect at least two of the circuit elements located on the substrate; (b) placing a non-conductive moisture resistant layer of at least about 1000 Angstroms onto the substrate and over the first metallization line(s); (c) placing a polyimide insulating layer onto the substrate formed in step (b) above; (d) applying a photoresist layer over the polyimide layer formed in step (c) above except over predetermined circuit elements; (e) etching the substrate to form via holes which expose the predetermined circuit elements; (f) placing a non-conductive moisture resistant layer onto the substrate formed in step (e) above; (g) applying a photoresist layer over all of the moisture resistant layer formed in step (f) above except over the predetermined circuit elements of step (d); (h) etching the substrate to form via holes which expose the predetermined circuit elements the via holes being of a smaller diameter than the via holes formed in step (e) above; (i) removing the photoresist layer; (j) placing second metallization line(s) onto the substrate so as to connect at least two of the predetermined circuit elements; (k) placing a non-conductive moisture resistant layer onto the substrate and over the second metallization line(s); (l) placing a polyimide insulating layer onto the substrate formed in step (k) above; and (m) repeat steps (d)-(l) until all of the metallization lines have been placed onto the substrate.

Claim 2

A method for retarding the corrosion of metallization lines in an integrated circuit comprising a silicon substrate having a passivation layer of silicon dioxide on the upper surface thereof, circuit elements located on the surface of the passivation layer, and multiple metallization lines placed on the substrate and are vertically spaced apart from each other by polyimide insulating layers which method comprises the steps of: (a) placing first metallization line(s) onto the surface of the passivation layer so as to connect at least two of the circuit elements located on the substrate; (b) placing a non-conductive moisture resistant layer of at least about 1000 Angstroms onto the substrate and over the first metallization line(s); (c) placing a polyimide insulating layer onto the substrate formed in step (b) above; (d) applying a photoresist layer over the polyimide layer formed in step (c) above except over predetermined circuit elements; (e) etching the substrate to form via holes which expose the predetermined circuit elements; (f) placing a non-conductive moisture resistant layer onto the substrate formed in step (e) above; (g) applying a photoresist layer over all of the moisture resistant layer formed in step (f) above except over the predetermined circuit elements of step (d); (h) etching the substrate to form via holes which expose the predetermined circuit elements the via holes being of a smaller diameter than the via holes formed in step (e) above; (i) removing the photoresist layer; (j) placing second metallization line(s) onto the substrate so as to connect at least two of the predetermined circuit elements; (k) placing a non-conductive moisture resistant layer onto the substrate and over the second metallization line(s); (l) placing a polyimide insulating layer onto the substrate formed in step (k) above; and (m) repeat steps (d)-(l) until all of the metallization lines have been placed onto the substrate.

Claim 6

A method for retarding the corrosion of metallization lines in an integrated circuit comprising a silicon substrate having a passivation layer of silicon dioxide on the upper surface thereof, circuit elements located on the surface of the passivation layer, and multiple metallization lines placed on the substrate and are vertically spaced apart from each other by polyimide insulating layers which method comprises the steps of: (a) placing first metallization line(s) onto the surface of the passivation layer so as to connect at least two of the circuit elements located on the substrate; (b) placing a conductive moisture resistant layer of at least about 1000 Angstroms onto the substrate and over the first metallization line(s); (c) etching the conductive moisture resistant layers placed onto the substrate in step (b) from the substrate, except in the area of the metallization lines so as to leave at least about 1000 Angstroms around each of the metallization lines formed; (d) placing a polyimide insulating layer onto the substrate formed in step (c) above; (e) applying a photoresist layer over the polyimide layer formed in step (d) above except over predetermined circuit elements; (f) etching the substrate to form via holes which expose the predetermined circuit elements; (g) placing a conductive moisture resistant layer onto the substrate formed in step (f) above; (h) etching the conductive moisture resistant layers placed onto the substrate in step (g) from the substrate, except in the area of the metallization line so as to leave at least about 1000 Angstroms around each of the metallization lines to be formed in step (j) below; (i) applying a photoresist layer over all of the substrate surface formed in step (h) above except over the predetermined circuit elements of step (e); (j) etching the substrate to form via holes which expose the predetermined circuit elements the via holes being of a smaller diameter than the via holes formed in step (f) above; (k) removing the photoresist layer; (l) placing second metallization line(s) onto the substrate so as to connect at least two of the predetermined circuit elements; (m) placing a conductive moisture resistant layer onto the substrate and over the second metallization line(s); (n) etching the conductive moisture resistant layers placed onto the substrate in step (m) from the substrate, except in the area of the metallization line so as to leave at least about 1000 Angstroms around each of the metallization lines to be formed in step (l); (o) placing a polyimide insulating layer onto the substrate formed in step (m) above; and (p) repeat steps (d)-(o) until all of the metallization lines have been placed onto the substrate.

Claim 7

A method for retarding the corrosion of metallization lines in an integrated circuit comprising a silicon substrate having a passivation layer of silicon dioxide on the upper surface thereof, circuit elements located on the surface of the passivation layer, and multiple metallization lines placed on the substrate and are vertically spaced apart from each other by polyimide insulating layers which method comprises the steps of: (a) placing first metallization line(s) onto the surface of the passivation layer so as to connect at least two of the circuit elements located on the substrate; (b) placing a conductive moisture resistant layer of at least about 1000 Angstroms onto the substrate and over the first metallization line(s); (c) etching the conductive moisture resistant layers placed onto the substrate in step (b) from the substrate, except in the area of the metallization lines so as to leave at least about 1000 Angstroms around each of the metallization lines formed; (d) placing a polyimide insulating layer onto the substrate formed in step (c) above; (e) applying a photoresist layer over the polyimide layer formed in step (d) above except over predetermined circuit elements; (f) etching the substrate to form via holes which expose the predetermined circuit elements; (g) placing a conductive moisture resistant layer onto the substrate formed in step (f) above; (h) etching the conductive moisture resistant layers placed onto the substrate in step (g) from the substrate, except in the area of the metallization line so as to leave at least about 1000 Angstroms around each of the metallization lines to be formed in step (j) below; (i) applying a photoresist layer over all of the substrate surface formed in step (h) above except over the predetermined circuit elements of step (e); (j) etching the substrate to form via holes which expose the predetermined circuit elements the via holes being of a smaller diameter than the via holes formed in step (f) above; (k) removing the photoresist layer; (l) placing second metallization line(s) onto the substrate so as to connect at least two of the predetermined circuit elements; (m) placing a conductive moisture resistant layer onto the substrate and over the second metallization line(s); (n) etching the conductive moisture resistant layers placed onto the substrate in step (m) from the substrate, except in the area of the metallization line so as to leave at least about 1000 Angstroms around each of the metallization lines to be formed in step (l); (o) placing a polyimide insulating layer onto the substrate formed in step (m) above; and (p) repeat steps (d)-(o) until all of the metallization lines have been placed onto the substrate.