US4661204A
Expired / Lapsed
US
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Method for forming vertical interconnects in polyimide insulating layers
Assignee: Hewlett Packard Development Co LP
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Filing: 1985-10-25
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Granted: 1987-04-28
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Expires: 2005-10-25
Abstract
Abstract A method for forming multiple metallization layers on a semiconductor wafer comprises applying insulating polyimide layers between adjacent metallization layers. Vertical interconnect holes are formed through the polyimide insulating layers using a positive photoresist mask. The vertical interconnect holes are etched using a fluorocarbon- or fluorosilicon-oxygen plasma under power and temperature conditions which provide for selectively etching the polyimide relative to the photoresist. By initially forming the plasma etch at high power conditions which reduce the selectivity for the polyimide, the upper portion of the vertical interconnect hole walls may be flared to reduce problems with step metallization. The remaining portion of the plasma etch, however, is performed under conditions which are more highly selective for the polyimide which provides for better dimensional control and eliminates formation of a contaminating layer at the bottom of the vertical interconnect hole.
Inventors
- 👤 Vishnu Mathur
- 👤 Socorro Garcia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:35
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/004; G03F7/09; G03F7/094; H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/286; H10P50/287; H10P50/73; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
90 words
A method for forming vertical interconnect holes in a polyimide layer on a semiconductor substrate, said method comprising: applying a positive photoresist layer having a thickness greater than the polyimide layer directly over the polyimide layer: exposing and developing the photoresist layer in a predetermined pattern corresponding to the desired pattern of vertical holes in the polyimide layer; and etching the vertical holes with a fluorocarbon- or fluorosilicon-oxygen plasma under pressure and power conditions selected to provide an etch ratio of the polyimide to the photoresist is at least 2:1.
Claim 2
Independent Claim
90 words
A method for forming vertical interconnect holes in a polyimide layer on a semiconductor substrate, said method comprising: applying a positive photoresist layer having a thickness greater than the polyimide layer directly over the polyimide layer: exposing and developing the photoresist layer in a predetermined pattern corresponding to the desired pattern of vertical holes in the polyimide layer; and etching the vertical holes with a fluorocarbon- or fluorosilicon-oxygen plasma under pressure and power conditions selected to provide an etch ratio of the polyimide to the photoresist is at least 2:1.
Claim 3
Dependent Claim
25 words
A method as in claim 1, wherein the etching is first carried out at a high etch rate and thereafter at a lower etch rate.
Claim 4
Dependent Claim
46 words
A method as in claim 2, wherein the plasma etch occurs in a parallel plate reactor at low pressure initially at a power level in the range from 250 to 350 watts and thereafter at a power level in the range from 50 to 150 watts.
Claim 5
Dependent Claim
30 words
A method as in claim 1, wherein fluorocarbon or fluorosilicon plasma is selected from the group consisting of CF 4 , C 2 F 6 , and SF 6 .
Claim 6
Dependent Claim
27 words
A method as in claim 1, wherein the volume ratio of fluorocarbon or fluorosilicon to oxygen in the plasma is in the range from 2:1 to 1:2.
Claim 7
Dependent Claim
23 words
A method as in claim 5, wherein the volume ratio of fluorocarbon or fluorosilicon to oxygen ratio in the plasma is about 1:1.
Claim 8
Independent Claim
131 words
A method for forming multiple metallization layers on a semiconductor substrate, said method comprising: forming a first metallization layer having a predefined interconnect pattern on the substrate; applying a first polyimide insulating layer over the first metallization layer; applying a positive photoresist layer having a thickness greater than the polyimide layer directly over the first polyimide insulating layer; exposing and developing the photoresist layer in a predetermined pattern corresponding to a desired pattern of vertical interconnects through the insulating layer; etching vertical holes through the polyimide insulating layer with a fluorocarbon- or fluorosilicon-oxygen plasma under pressure and power conditions such that the etch ratio of the polyimide to the photoresist is at least 2:1; and forming a second metallization layer having a predefined interconnect pattern over the first polyimide insulating layer.
Claim 9
Independent Claim
131 words
A method for forming multiple metallization layers on a semiconductor substrate, said method comprising: forming a first metallization layer having a predefined interconnect pattern on the substrate; applying a first polyimide insulating layer over the first metallization layer; applying a positive photoresist layer having a thickness greater than the polyimide layer directly over the first polyimide insulating layer; exposing and developing the photoresist layer in a predetermined pattern corresponding to a desired pattern of vertical interconnects through the insulating layer; etching vertical holes through the polyimide insulating layer with a fluorocarbon- or fluorosilicon-oxygen plasma under pressure and power conditions such that the etch ratio of the polyimide to the photoresist is at least 2:1; and forming a second metallization layer having a predefined interconnect pattern over the first polyimide insulating layer.
Claim 10
Dependent Claim
31 words
A method as in claim 7, wherein the first polyimide layer is applied by spinning and curing polyamic acid to a final thickness in the range from 0.8 to 2.5 μm.
Claim 11
Dependent Claim
26 words
A method as in claim 7, wherein the positive photoresist layer is applied by spinning to a thickness in the range from 2.0 to 3.0 μm.
Claim 12
Dependent Claim
25 words
A method as in claim 7, wherein the etching is first carried out at a high etch rate and thereafter at a low etch rate.
Claim 13
Dependent Claim
43 words
A method as in claim 10, wherein the plasma etch occurs in a parallel plate reactor at low pressure initially at a power level in the range from 250 to 350 watts and thereafter at a power level from 50 to 150 watts.
Claim 14
Dependent Claim
31 words
A method as in claim 7, wherein the fluorocarbon- or fluorosilicon-oxygen plasma is selected from the group consisting of CF 4 , C 2 F 6 , and SF 6 .
Claim 15
Dependent Claim
27 words
A method as in claim 7, wherein the volume ratio of fluorocarbon or fluorosilicon to oxygen in the plasma is in the range from 2:1 to 1:2.
Claim 16
Dependent Claim
23 words
A method as in claim 13, wherein the volume ratio of fluorocarbon or fluorosilicon to oxygen ratio in the plasma is about 1:1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-27 | 1990-10-27 | 1991-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-27 | 1994-10-27 | 1995-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-27 | 1998-10-27 | 1999-04-28 | $7700.00 | Window Closed / Lapsed |