Multimode input circuit receiving two signals having amplitude variations different from each other

Claim 2

A multimode input circuit comprising: an input terminal; first outputting means, including a buffer circuit, for receiving a first signal having a first amplitude variation via the input terminal and outputting the first signal of a preset potential; second outputting means for receiving a second signal having a second amplitude variation different from the first amplitude variation via the input terminal and outputting third signal of a preset potential, the second outputting means including a power source supplying terminal for supplying the same potential as the maximum potential of the second signal, a first FET having a source connected to the power source supplying terminal, a gate supplied with a selection signal for specifying one of the input signals to be selected by the multimode input circuit and a drain, and a second FET formed to make a complementary structure together with the first FET and having a drain connected to the drain of the first FET, a gate connected to the input terminal and a source connected to a circuit ground; and selecting means for receiving the first and third signals from the first and second outputting means and a selection signal from the exterior and selecting and outputting one of the first and third signals according to the state of the selection signal.

Claim 3

A multimode input circuit according to claim 1, wherein the third signal is a digital signal having substantially the same amplitude variation as that of the first signal and having the same logic value as the second signal.

Claim 4

A multimode input circuit according to claim 1, wherein the second FET is a high-withstand voltage logic FET.

Claim 5

A multimode input circuit according to claim 1, wherein the selecting means includes a first gate circuit which is activated by the selection signal, for receiving a first signal output from the first outputting means and a second gate circuit which is activated when the selection signal is set in an inverted form of the first gate signal, for receiving the third signal from the second outputting means.

Claim 6

A multimode input circuit according to claim 1, wherein the amplitude of the first signal is 5 V and the amplitude of the second signal is 12 V.

Claim 7

A multimode input circuit comprising: an input terminal; first outputting means including a buffer circuit, for receiving a first signal having an amplitude variation of 5 V via the input terminal and outputting the first signal of a preset potential; second outputting means for receiving a second signal having an amplitude variation of 12 via the input terminal and outputting a digital signal as a third signal having an amplitude variation of 5 V and having the same logic value as the second signal, the second outputting means including a power source supplying terminal of 12 V, a first FET having a source connected to the power source supplying terminal, a gate supplied with a selection signal for specifying one of the input signals to be selected by the multimode input circuit and a drain, and a second FET formed to make a complementary structure together with the first FET and having a drain connected to the drain of the first FET, a gate connected to the input terminal and a source connected to a circuit ground; and selecting means for receiving the first and third signals from the first and second outputting means and a selection signal from the exterior and selecting and outputting one of the first and third signals according to the state of the selection signal, the selecting means including a first gate circuit which is activated by the selection signal, for receiving the first signal output from the first outputting means and a second gate circuit which is activated when the selection signal is set in an inverted form of the first gate signal, for receiving the third signal from the second outputting means.

Claim 8

A multimode input circuit comprising: an input terminal; first outputting means including a buffer circuit, for receiving a first signal having an amplitude variation of 5 V via the input terminal and outputting the first signal of a preset potential; second outputting means for receiving a second signal having an amplitude variation of 12 via the input terminal and outputting a digital signal as a third signal having an amplitude variation of 5 V and having the same logic value as the second signal, the second outputting means including a power source supplying terminal of 12 V, a first FET having a source connected to the power source supplying terminal, a gate supplied with a selection signal for specifying one of the input signals to be selected by the multimode input circuit and a drain, and a second FET formed to make a complementary structure together with the first FET and having a drain connected to the drain of the first FET, a gate connected to the input terminal and a source connected to a circuit ground; and selecting means for receiving the first and third signals from the first and second outputting means and a selection signal from the exterior and selecting and outputting one of the first and third signals according to the state of the selection signal, the selecting means including a first gate circuit which is activated by the selection signal, for receiving the first signal output from the first outputting means and a second gate circuit which is activated when the selection signal is set in an inverted form of the first gate signal, for receiving the third signal from the second outputting means.

Claim 9

A liquid crystal display system comprising: a liquid crystal display; means for generating signals for operating the liquid crystal display; a plurality of means connected to the liquid crystal display, for driving the liquid crystal display; and a plurality of multimode input circuits respectively connected to the plurality of driving means and having: an input terminal connected to the generating means; first outputting means including a buffer circuit, for receiving a first signal having an amplitude variation of 5 V via the input terminal and outputting the first signal of a preset potential; second outputting means for receiving a second signal having an amplitude variation of 12 V via the input terminal and outputting a digital signal as a third signal having an amplitude variation of 5 V and having the same logic value as the second signal, the second outputting means including a power source supplying terminal of 12 V, a first FET having a source connected to the power source supplying terminal, a gate supplied with a selection signal for specifying one of the input signals to be selected by the multimode input circuit and a drain, and a second FET formed to make a complementary structure together with the first FET and having a drain connected to the drain of the first FET, a gate connected to the input terminal and a source connected to a circuit ground; and selecting means for receiving the first and third signals from the first and second outputting means and a selection signal from the exterior and selecting and outputting one of the first and third signals according to the state of the selection signal, the selecting means including a first gate circuit which is activated by the selection signal, for receiving the first signal output from the first outputting means and a second gate circuit which is activated when the selection signal is set in an inverted form of the first gate signal, for receiving the third signal from the second outputting means.

Claim 10

A liquid crystal display system comprising: a liquid crystal display; means for generating signals for operating the liquid crystal display; a plurality of means connected to the liquid crystal display, for driving the liquid crystal display; and a plurality of multimode input circuits respectively connected to the plurality of driving means and having: an input terminal connected to the generating means; first outputting means including a buffer circuit, for receiving a first signal having an amplitude variation of 5 V via the input terminal and outputting the first signal of a preset potential; second outputting means for receiving a second signal having an amplitude variation of 12 V via the input terminal and outputting a digital signal as a third signal having an amplitude variation of 5 V and having the same logic value as the second signal, the second outputting means including a power source supplying terminal of 12 V, a first FET having a source connected to the power source supplying terminal, a gate supplied with a selection signal for specifying one of the input signals to be selected by the multimode input circuit and a drain, and a second FET formed to make a complementary structure together with the first FET and having a drain connected to the drain of the first FET, a gate connected to the input terminal and a source connected to a circuit ground; and selecting means for receiving the first and third signals from the first and second outputting means and a selection signal from the exterior and selecting and outputting one of the first and third signals according to the state of the selection signal, the selecting means including a first gate circuit which is activated by the selection signal, for receiving the first signal output from the first outputting means and a second gate circuit which is activated when the selection signal is set in an inverted form of the first gate signal, for receiving the third signal from the second outputting means.