Dynamic random access memory

Claim 2

A dynamic random access memory comprising: a plurality of dynamic memory cells arranged in rows and columns; a plurality of word lines each connected to the dynamic memory cells arranged in a corresponding one of the rows; a plurality of bit lines each connected to the dynamic memory cells arranged in a corresponding one of the columns; and a plurality of noise-eliminating circuits each having a first terminal connected to a corresponding one of the word lines, a second terminal connected to a node for supplying an earth voltage during a normal operation and a stress voltage during a stress test, and a transfer means, responsive to a first transfer signal for selectively transferring the stress voltage from the second terminal to the first terminal during a stress test, and responsive to a second transfer signal for selectively connecting the first terminal to the earth voltage during normal operation.

Claim 3

A dynamic random access memory comprising: a plurality of dynamic memory cells arranged in rows and columns; a plurality of word lines each connected to the dynamic memory cells arranged in a corresponding one of the rows; a plurality of bit lines each connected to the dynamic memory cells arranged in a corresponding one of the columns; a plurality of word line-selecting circuits each for outputting a word line-selecting signal in accordance with an address signal supplied from outside the dynamic random access memory or from an element incorporated in the dynamic random access memory; a plurality of word line-driving circuits, each connected between a word line-driving power source and an end of a corresponding one of the word lines, for driving the corresponding word line in accordance with a signal output from a corresponding one of the word line-selecting circuits; a plurality of bit line-precharge circuits each connected between a corresponding one of the bit lines and a bit line-precharge power source line, the bit line-precharge circuits being controlled by bit line-precharge signals; a bit line-precharge voltage-generating circuit for supplying a bit line-precharge voltage to the bit line-precharge power source line; and a plurality of noise-eliminating circuits each having a first terminal connected to a corresponding one of the word lines, a second terminal connected to a node for supplying an earth voltage during a normal operation and a stress voltage during a stress test, and a transfer means, responsive to a first transfer signal for selectively transferring the stress voltage from the second terminal to the first terminal during a stress test, and responsive to an output of a corresponding one of the word line-selecting circuits during a normal operation for selectively connecting the first terminal to the earth voltage.

Claim 4

A dynamic random access memory comprising: a plurality of dynamic memory cells arranged in rows and columns; a plurality of word lines each connected to the dynamic memory cells arranged in a corresponding one of the rows; a plurality of bit lines each connected to the dynamic memory cells arranged in a corresponding one of the columns; a plurality of word line-selecting circuits each for outputting a word line-selecting signal in accordance with an address signal supplied from outside the dynamic random access memory or from an element incorporated in the dynamic random access memory; a plurality of word line-driving circuits, each connected between a word line-driving power source and an end of a corresponding one of the word lines, for driving the corresponding word line in accordance with a signal output from a corresponding one of the word line-selecting circuits; a plurality of bit line-precharge circuits each connected between a corresponding one of the bit lines and a bit line-precharge power source line, the bit line-precharge circuits being controlled by bit line-precharge signals; a bit line-precharge voltage-generating circuit for supplying a bit line-precharge voltage to the bit line-precharge power source line; and a plurality of noise-eliminating circuits each having a first terminal connected to a corresponding one of the word lines, a second terminal connected to a node for supplying an earth voltage during a normal operation and a stress voltage during a stress test, and a transfer means, responsive to a first transfer signal for selectively transferring the stress voltage from the second terminal to the first terminal during a stress test, and responsive to an output of a corresponding one of the word line-selecting circuits during a normal operation for selectively connecting the first terminal to the earth voltage.

Claim 5

The dynamic random access memory according to claim 1, further comprising a third terminal connected to the second terminal of all of the noise-eliminating circuits, the third terminal being supplied with the stress voltage from outside the dynamic random access memory at the time of the stress test.

Claim 6

The dynamic random access memory according to claim 2, further comprising a third terminal connected to the second terminal of all of the noise-eliminating circuits, the third terminal being supplied with the stress voltage from outside the dynamic random access memory at the time of the stress test.

Claim 7

The dynamic random access memory according to claims 3 or 4, further comprising a resistor element connected between the third terminal and the earth voltage.

Claim 8

The dynamic random access memory according to any one of claims 1 to 4, further comprising a fourth terminal for supplying a control voltage for turning on the noise-eliminating circuits.

Claim 9

The dynamic random access memory according to claim 6, further comprising a resistor element connected between the fourth terminal and a power source potential node, and a resistor element connected between the third terminal and the earth voltage.

Claim 10

The dynamic random access memory according to claim 5, further comprising a fourth terminal for supplying a control voltage for turning on the noise-eliminating circuits.

Claim 11

The dynamic random access memory according to claim 8, further comprising a resistor element connected between the fourth terminal and a power source potential node.

Claim 12

The dynamic random access memory according to claim 1, further comprising a bit line potential control means for controlling a potential of a bit line-precharge power line at the time of the voltage stress test.

Claim 13

The dynamic random access memory according to claims 2 or 4, further comprising a bit line potential control means for controlling a potential of the bit line-precharge power source line at the time of the stress test.

Claim 14

The dynamic random access memory according to claim 11, wherein the bit line potential control means turns off the bit line-precharge voltage-generating circuit at the time of the stress test, thereby transmitting a bit line potential, supplied from outside the dynamic random access memory, to the bit line-precharge power line, or turns off the bit line precharge voltage-generating circuit, thereby connecting the bit line-precharge power source line to a predetermined potential terminal.

Claim 15

The dynamic random access memory according to claim 12, further comprising a plate potential-generating circuit for supplying a plate potential to a capacitor plate of the dynamic memory cells, and plate potential control means for controlling the output of the plate potential-generating circuit at the time of the stress test.

Claim 16

The dynamic random access memory according to claim 13, wherein the plate potential control means turns off, at the time of the stress test, the plate potential-generating circuit, thereby transmitting the plate potential, input from outside the dynamic random access memory, to the capacitor plate of the dynamic memory cells, or turns off, at the time of the stress test, the plate potential-generating circuit, thereby connecting the capacitor plate to a predetermined potential terminal.

Claim 17

A semiconductor memory device, comprising: memory cells arranged in a row and column array; word lines each connecting memory cells in a respective row of said array; bit lines each connecting memory cells in a respective column of said array; nodes each supplying an earth voltage during a normal operation of said semiconductor memory device and a stress voltage during a stress test operation of said semiconductor memory device; word line driving circuits each connected to a corresponding one of said word lines and including driving means responsive to word line selecting signals for selectively driving the corresponding word line, a noise-eliminating circuit connected between one of said nodes and the corresponding word line, and control means, responsive to the word line selecting signals during the normal operation for selectively coupling the corresponding word line to the earth voltage and responsive to a stress test signal during the stress test operation for coupling the corresponding word line to the stress voltage; and word line selecting circuits coupled to said word line driving circuits, said word line selecting circuits responsive to address data during the normal operation for generating word line selection signals supplied to said driving means.

Claim 18

A semiconductor memory device, comprising: memory cells arranged in a row and column array; word lines each connecting memory cells in a respective row of said array; bit lines each connecting memory cells in a respective column of said array; nodes each supplying an earth voltage during a normal operation of said semiconductor memory device and a stress voltage during a stress test operation of said semiconductor memory device; word line driving circuits each connected to a corresponding one of said word lines and including driving means responsive to word line selecting signals for selectively driving the corresponding word line, a noise-eliminating circuit connected between one of said nodes and the corresponding word line, and control means, responsive to the word line selecting signals during the normal operation for selectively coupling the corresponding word line to the earth voltage and responsive to a stress test signal during the stress test operation for coupling the corresponding word line to the stress voltage; and word line selecting circuits coupled to said word line driving circuits, said word line selecting circuits responsive to address data during the normal operation for generating word line selection signals supplied to said driving means.

Claim 19

The semiconductor memory device according to claim 15, wherein said noise-eliminating circuit comprises a transistor having a first terminal connected to the corresponding one of said word lines, a second terminal connected to one of said nodes, and a control terminal.

Claim 20

The semiconductor memory device according to claim 15, wherein said nodes comprise a pad for contacting probes of a probe card.

Claim 21

The semiconductor memory device according to claim 15, wherein said nodes comprise a pad connected to an earth potential for contacting probes of a probe card.

Claim 22

A dynamic random access memory comprising: a plurality of dynamic memory cells arranged in rows and columns; a plurality of word lines each connected to the dynamic memory cells arranged in a corresponding one of the rows; a plurality of bit lines each connected to the dynamic memory cells arranged in a corresponding one of the columns; a plurality of word line-selecting circuits each for outputting a word line-selecting signal in accordance with an address signal supplied from outside the dynamic random access memory or from an element incorporated in the dynamic random access memory; a plurality of word line-driving circuits, each connected between a word line-driving power source and an end of a corresponding one of the word lines, for driving the corresponding word line in accordance with a signal output from a corresponding one of the word line-selecting circuits; a plurality of bit line-precharge circuits each connected between a corresponding one of the bit lines and a bit line-precharge power source line, the bit line-precharge circuits being controlled by bit line-precharge signals; a bit line-precharge voltage-generating circuit for supplying a bit line-precharge voltage to the bit line-precharge power source line; and a plurality of noise-eliminating circuits each having a first terminal connected to a corresponding one of the word lines, a second terminal connected to a node for supplying an earth voltage during a normal operation and a stress voltage during a stress test, and a transfer means, responsive to a stress test signal and a precharge signal, for selectively transferring the stress voltage from the second terminal to the first terminal during the stress test and selectively connecting the first terminal to the earth voltage during the normal operation.

Claim 23

A dynamic random access memory comprising: a plurality of dynamic memory cells arranged in rows and columns; a plurality of word lines each connected to the dynamic memory cells arranged in a corresponding one of the rows; a plurality of bit lines each connected to the dynamic memory cells arranged in a corresponding one of the columns; a plurality of word line-selecting circuits each for outputting a word line-selecting signal in accordance with an address signal supplied from outside the dynamic random access memory or from an element incorporated in the dynamic random access memory; a plurality of word line-driving circuits, each connected between a word line-driving power source and an end of a corresponding one of the word lines, for driving the corresponding word line in accordance with a signal output from a corresponding one of the word line-selecting circuits; a plurality of bit line-precharge circuits each connected between a corresponding one of the bit lines and a bit line-precharge power source line, the bit line-precharge circuits being controlled by bit line-precharge signals; a bit line-precharge voltage-generating circuit for supplying a bit line-precharge voltage to the bit line-precharge power source line; and a plurality of noise-eliminating circuits each having a first terminal connected to a corresponding one of the word lines, a second terminal connected to a node for supplying an earth voltage during a normal operation and a stress voltage during a stress test, and a transfer means, responsive to a stress test signal and a precharge signal, for selectively transferring the stress voltage from the second terminal to the first terminal during the stress test and selectively connecting the first terminal to the earth voltage during the normal operation.