Semiconductor memory including means for noise suppression

Claim 2

A semiconductor memory comprising: a reference potential generating circuit; a first data line adapted to be supplied with a reference potential from said reference potential generating circuit; a second data line paired with said first data line and adapted to be supplied with said reference potential from said reference potential generating circuit; a word line adapted to be fed with a selection signal; a dummy word line adapted to be fed with a drive signal which is synchronized with said selection signal; a dynamic memory cell coupled to said word line and to said first data line, and including an address selecting MOSFET and an information storing capacitor, wherein said dynamic memory cell sets the potential of said first data line at a higher or lower level than the reference potential at said second data line when said dynamic memory cell is selected by said selection signal being fed to said word line; a sense amplifier for amplifying a level difference which occurs between said first data line and said second data line when said dynamic memory cell is selected; and a dummy capacitor which is coupled between one of said second or first data lines and said dummy word line and which imparts noise to said one of said second or first data line in response to said drive signal being fed to said dummy word line to reduce noise between said first and second data lines which is caused by operation of said address selecting MOSFET when said dynamic memory cell is selected. wherein said dummy capacitor comprises a MOS capacitor, wherein said MOS capacitor comprises a MOSFET having a gate electrode coupled to said dummy word line and a current carrying electrode coupled to said second or first data line, and wherein the MOSFET acting as said MOS capacitor is a depletion mode MOSFET.

Claim 3

A semiconductor memory according to claim 4, wherein said dummy capacitor is connected between said dummy word line and said second data line, and wherein said drive signal is raised to a high level in synchronism with a rise of said selection signal to a high level.

Claim 4

A semiconductor memory comprising: a reference potential generating circuit; a first data line adapted to be supplied with a reference potential from said reference potential generating circuit; a second data line paired with said first data line and adapted to be supplied with said reference potential from said reference potential generating circuit; a word line adapted to be fed with a selection signal; a dummy word line adapted to be fed with a drive signal which is synchronized with said selection signal; a dynamic memory cell coupled to said word line and to said first data line, and including an address selecting MOSFET and an information storing capacitor, wherein said dynamic memory cell sets the potential of said first data line at a higher or lower level than the reference potential at said second data line when said dynamic memory cell is selected by said selection signal being fed to said word line; a sense amplifier for amplifying a level difference which occurs between said first data line and said second data line when said dynamic memory cell is selected; and a dummy capacitor which is coupled between one of said second or first data lines and said dummy word line and which imparts noise to said one of said second or first data line in response to said drive signal being fed to said dummy word line to reduce noise between said first and second data line which is caused by operation of said address selecting MOSFET when said dynamic memory cell is selected; wherein said dummy capacitor comprises a MOS capacitor, wherein said dummy capacitor is connected between said dummy word line and said second data line, wherein said drive signal is raised to a high level in synchronism with a rise of said selection signal to a high level, and wherein said reference potential generating circuit includes a switching element for short-circuiting said first and second data lines to generate said reference potential.

Claim 5

A semiconductor memory comprising: a reference potential generating circuit; a first data line adapted to be supplied with a reference potential from said reference potential generating circuit; a second data line paired with said first data line and adapted to be supplied with said reference potential from said reference potential generating circuit; a word line adapted to be fed with a selection signal; a dummy word line adapted to be fed with a drive signal which is synchronized with said selection signal; a dynamic memory cell coupled to said word line and to said first data line, and including an address selecting MOSFET and an information storing capacitor, wherein said dynamic memory cell sets the potential of said first data line at a higher or lower level than the reference potential at said second data line when said dynamic memory cell is selected by said selection signal being fed to said word line; a sense amplifier for amplifying a level difference which occurs between said first data line and said second data line when said dynamic memory cell is selected; and a dummy capacitor which is coupled between one of said second or first data lines and said dummy word line and which imparts noise to said one of said second or first data line in response to said drive signal being fed to said dummy word line to reduce noise between said first and second data line which is caused by operation of said address selecting MOSFET when said dynamic memory cell is selected; wherein said dummy capacitor comprises a MOS capacitor, wherein said dummy capacitor is connected between said dummy word line and said second data line, wherein said drive signal is raised to a high level in synchronism with a rise of said selection signal to a high level, and wherein said reference potential generating circuit includes a switching element for short-circuiting said first and second data lines to generate said reference potential.

Claim 6

A semiconductor memory according to claim 3, wherein said first and second data lines have data line capacitances substantially equal to each other; and wherein said dummy capacitor element capacitance has less than a gate capacitance of said address selecting MOSFET in an ON state.

Claim 7

A semiconductor memory according to claim 3, wherein said dummy capacitor includes a MOSFET having a gate electrode coupled to said dummy word line and a current transfer electrode coupled to said second data line.

Claim 8

A semiconductor memory according to claim 5, wherein the MOSFET acting as said dummy capacitor is a depletion mode MOSFET and has less gate capacitance than a gate capacitance of said address selecting MOSFET in an ON state.

Claim 9

A semiconductor memory according to claim 5, wherein said address selecting MOSFET and said MOSFET acting as said dummy capacitor each have gate electrodes occupying predetermined areas on a major surface of a semiconductor body on which said semiconductor memory is formed, and further wherein the MOSFET acting as said dummy capacitor is a depletion mode MOSFET and has a smaller gate electrode area than the gate electrode area of said address selecting MOSFET.

Claim 10

A semiconductor memory according to claim 7, wherein the gate electrode area of the MOSFET acting as said dummy capacitive element is half as large as the gate electrode area of said address selecting MOSFET.

Claim 11

A semiconductor memory according to claim 7, wherein said first and second data lines constitute together the data line of one memory array.

Claim 12

A semiconductor memory according to claim 1, wherein said dummy capacitive element is connected between said dummy word line and said first data line, and wherein said drive signal is charged to a predetermined level from a high level in synchronism with the rise of said selection signal to a high level.

Claim 13

A semiconductor memory comprising: a reference potential generating circuit; a first data line adapted to be supplied with a reference potential from said reference potential generating circuit; a second data line paired with said first data line and adapted to be supplied with said reference potential from said reference potential generating circuit; a word line adapted to be fed with a selection signal; a dummy word line adapted to be fed with a drive signal which is synchronized with said selection signal; a dynamic memory cell coupled to said word line and to said first data line, and including an address selecting MOSFET and an information storing capacitor, wherein said dynamic memory cell sets the potential of said first data line at a higher or lower level than the reference potential at said second data line when said dynamic memory cell is selected by said selection signal being fed to said word line; a sense amplifier for amplifying a level difference which occurs between said first data line and said second data line when said dynamic memory cell is selected; and a dummy capacitor which is coupled between one of said second or first data lines and said dummy word line and which imparts noise to said one of said second or first data line in response to said drive signal being fed to said dummy word line to reduce noise between said first and second data lines which is caused by operation of said address selecting MOSFET when said dynamic memory cell is selected, wherein said dummy capacitor comprises a MOS capacitor, wherein said dummy capacitive element is connected between said dummy word line and said first data line, wherein said drive signal is changed to a predetermined level from a high level in synchronism with the rise of said selection signal to a high level, and wherein said reference potential generating circuit includes a switching element for short-circuiting said first and second data lines to generate said reference potential.

Claim 14

A semiconductor memory comprising: a reference potential generating circuit; a first data line adapted to be supplied with a reference potential from said reference potential generating circuit; a second data line paired with said first data line and adapted to be supplied with said reference potential from said reference potential generating circuit; a word line adapted to be fed with a selection signal; a dummy word line adapted to be fed with a drive signal which is synchronized with said selection signal; a dynamic memory cell coupled to said word line and to said first data line, and including an address selecting MOSFET and an information storing capacitor, wherein said dynamic memory cell sets the potential of said first data line at a higher or lower level than the reference potential at said second data line when said dynamic memory cell is selected by said selection signal being fed to said word line; a sense amplifier for amplifying a level difference which occurs between said first data line and said second data line when said dynamic memory cell is selected; and a dummy capacitor which is coupled between one of said second or first data lines and said dummy word line and which imparts noise to said one of said second or first data line in response to said drive signal being fed to said dummy word line to reduce noise between said first and second data lines which is caused by operation of said address selecting MOSFET when said dynamic memory cell is selected, wherein said dummy capacitor comprises a MOS capacitor, wherein said dummy capacitive element is connected between said dummy word line and said first data line, wherein said drive signal is changed to a predetermined level from a high level in synchronism with the rise of said selection signal to a high level, and wherein said reference potential generating circuit includes a switching element for short-circuiting said first and second data lines to generate said reference potential.

Claim 15

A semiconductor memory comprising: a reference potential generating circuit; a first data line adapted to be supplied with a reference potential from said reference potential generating circuit; a second data line paired with said first data line and adapted to be supplied with said reference potential from said reference potential generating circuit; a word line adapted to be fed with a selection signal; a dummy word line adapted to be fed with a drive signal which is synchronized with said selection signal; a dynamic memory cell coupled to said word line and to said first data line, and including an address selecting MOSFET and an information storing capacitor, wherein said dynamic memory cell sets the potential of said first data line at a higher or lower level than the reference potential at said second data line when said dynamic memory cell is selected by said selection signal being fed to said word line; a sense amplifier for amplifying a level difference which occurs between said first data line and said second data line when said dynamic memory cell is selected; and a dummy capacitor which is coupled between one of said second or first data lines and said dummy word line and which imparts noise to said one of said second or first data line in response to said drive signal being fed to said dummy word line to reduce noise between said first and second data lines which is caused by operation of said address selecting MOSFET when said dynamic memory cell is selected, wherein said dummy capacitor comprises a MOS capacitor, wherein said dummy capacitive element is connected between said dummy word line and said first data line, wherein said drive signal is changed to a predetermined level from a high level in synchronism with the rise of said selection signal to a high level, wherein said first and second data lines have data line capacitances substantially equal to each other, and wherein said dummy capacitor has less capacitance than the gate capacitance of said address selecting MOSFET in an ON state.

Claim 16

A semiconductor memory comprising: a reference potential generating circuit; a first data line adapted to be supplied with a reference potential from said reference potential generating circuit; a second data line paired with said first data line and adapted to be supplied with said reference potential from said reference potential generating circuit; a word line adapted to be fed with a selection signal; a dummy word line adapted to be fed with a drive signal which is synchronized with said selection signal; a dynamic memory cell coupled to said word line and to said first data line, and including an address selecting MOSFET and an information storing capacitor, wherein said dynamic memory cell sets the potential of said first data line at a higher or lower level than the reference potential at said second data line when said dynamic memory cell is selected by said selection signal being fed to said word line; a sense amplifier for amplifying a level difference which occurs between said first data line and said second data line when said dynamic memory cell is selected; and a dummy capacitor which is coupled between one of said second or first data lines and said dummy word line and which imparts noise to said one of said second or first data line in response to said drive signal being fed to said dummy word line to reduce noise between said first and second data lines which is caused by operation of said address selecting MOSFET when said dynamic memory cell is selected, wherein said dummy capacitor comprises a MOS capacitor, wherein said dummy capacitive element is connected between said dummy word line and said first data line, wherein said drive signal is changed to a predetermined level from a high level in synchronism with the rise of said selection signal to a high level, wherein said first and second data lines have data line capacitances substantially equal to each other, and wherein said dummy capacitor has less capacitance than the gate capacitance of said address selecting MOSFET in an ON state.

Claim 17

A semiconductor memory according to claim 11, wherein said dummy capacitor includes a MOSFET having a gate electrode coupled to said dummy word line and a current transfer electrode coupled to said first data line.

Claim 18

A semiconductor memory according to claim 13, wherein the MOSFET acting as said dummy capacitor is a depletion mode MOSFET and has less gate capacitance than that of said address selecting MOSFET in an ON state.

Claim 19

A semiconductor memory including a first data line, a second data line, reference voltage setting means coupled to said first and second data lines for presetting a predetermined reference potential at each of said first and second data lines, a word line which is fed with a selection signal, a memory cell which is coupled between said first data line and said word line, which has an address selecting MOSFET and a store capacitor and which, in response to said selection signal, varies the potential at said first data line in accordance with information stored in said store capacitor, and amplifier means coupled between said first and second data lines for amplifying a level difference between said predetermined reference potential at said second data line and the potential varied at said first data line, said semiconductor memory comprising: a signal line which is fed with a drive signal which is synchronized with said selection signal; and dummy capacitor means which is coupled between said signal line and said first and second data line and which imparts noise to said first or second data line in response to said drive signal to reduce noise between said first and second data lines which occurs because of noise imparted to said first data line through a gate capacitance of said address selecting MOSFET, wherein said dummy capacitor means includes a MOS capacitor, and wherein said MOS capacitor includes a MOSFET having a gate electrode coupled to said signal line and a current carrying electrode coupled to said first or second data line, and wherein said MOSFET is a depletion mode MOSFET.

Claim 20

A semiconductor memory including a first data line, a second data line, reference voltage setting means coupled to said first and second data lines for presetting a predetermined reference potential at each of said first and second data lines, a word line which is fed with a selection signal, a memory cell which is coupled between said first data line and said word line, which has an address selecting MOSFET and a store capacitor and which, in response to said selection signal, varies the potential at said first data line in accordance with information stored in said store capacitor, and amplifier means coupled between said first and second data lines for amplifying a level difference between said predetermined reference potential at said second data line and the potential varied at said first data line, said semiconductor memory comprising: a signal line which is fed with a drive signal which is synchronized with said selection signal; and dummy capacitor means which is coupled between said signal line and said first and second data line and which imparts noise to said first or second data line in response to said drive signal to reduce noise between said first and second data lines which occurs because of noise imparted to said first data line through a gate capacitance of said address selecting MOSFET, wherein said dummy capacitor means includes a MOS capacitor, and wherein said MOS capacitor includes a MOSFET having a gate electrode coupled to said signal line and a current carrying electrode coupled to said first or second data line, and wherein said MOSFET is a depletion mode MOSFET.

Claim 21

A semiconductor memory according to 15, wherein said MOS capacitor is coupled between said signal line and said second data line, and wherein said drive signal is raised to a high level in synchronism with the rise of said selection signal to a high level.

Claim 22

A semiconductor memory according to 15, wherein said MOS capacitor is coupled between said signal line and said second data line, and wherein said drive signal is raised to a high level in synchronism with the rise of said selection signal to a high level.

Claim 23

A semiconductor memory according to claim 15, wherein said MOS capacitor is coupled between said signal line and said first data line, and wherein said drive signal is changed to a low level from a high level in synchronism with the rise of said selection signal to a high level.

Claim 24

A semiconductor memory according to claim 16, wherein said MOS capacitor includes a MOSFET having a gate electrode coupled to said signal line and a current carrying electrode coupled to said second data line.

Claim 25

A semiconductor memory according to claim 17, wherein said MOS capacitor includes a MOSFET having a gate electrode coupled to said signal line and a current carrying electrode coupled to said first data line.

Claim 26

A semiconductor memory comprising: first and second data lines paired with each other and respectively coupled to a plurality of dynamic memory cells each including an address selecting MOSFET and an information storing capacitor; a plurality of word lines coupled to said plural dynamic memory cells; a reference potential generating circuit for supplying a reference potential to said first and second data lines; first and second dummy word lines; a first dummy capacitor connected between said first data line and said first dummy word line; a second dummy capacitor connected between said second data line and said second dummy word line; a word line driving circuit for selecting one of said plural memory cells coupled to said first and second data lines; a dummy word line driving circuit for feeding a drive signal to said first or second dummy word lines in synchronism with the operation of said word line driving circuit to select one of said dummy capacitors to impart noise respectively to either said first or said second data lines to reduce noise between the first and second data lines caused by a capacitance existing in said address selecting MOSFET; and a sense amplifier for amplifying a signal level difference applied between said first and second data lines.

Claim 27

A semiconductor memory comprising: first and second data lines paired with each other and respectively coupled to a plurality of dynamic memory cells each including an address selecting MOSFET and an information storing capacitor; a plurality of word lines coupled to said plural dynamic memory cells; a reference potential generating circuit for supplying a reference potential to said first and second data lines; first and second dummy word lines; a first dummy capacitor connected between said first data line and said first dummy word line; a second dummy capacitor connected between said second data line and said second dummy word line; a word line driving circuit for selecting one of said plural memory cells coupled to said first and second data lines; a dummy word line driving circuit for feeding a drive signal to said first or second dummy word lines in synchronism with the operation of said word line driving circuit to select one of said dummy capacitors to impart noise respectively to either said first or said second data lines to reduce noise between the first and second data lines caused by a capacitance existing in said address selecting MOSFET; and a sense amplifier for amplifying a signal level difference applied between said first and second data lines.