Memory circuit with noise preventing means for word lines

Claim 2

A memory circuit comprising first and second word lines adjacently arranged in parallel, a first driving means coupled to said first word line, a second driving means coupled to said second word line, a plurality of bit lines intersecting with said first and second word lines, a plurality of memory cells coupled between said word lines and said bit lines, and a noise preventing circuit coupled to said first and second word lines, said noise preventing circuit including a first field effect transistor coupled between said first word line and a reference voltage, means for connecting a gate of said first transistor to said second word line, a second field effect transistor coupled between said second word line and said reference voltage, and means for connecting a gate of said second transistor to said first word line.

Claim 3

The memory circuit according to claim 1, in which each of said first and second, driving means includes means for precharging a first node, a plurality of decoding field effect transistors coupled between said first node and said reference voltage in parallel, each of said decoding field effect transistors receiving an address signal at its gate, an output field effect transistor, means for connecting a gate of said output field effect transistor to said first node, means for connecting one of a drain and a source of said output field effect transistor to associated one of said word lines, and means for supplying the other of the drain and source of said output field effect transistor with a control signal.

Claim 4

The memory circuit according to claim 1, in which each of said memory cells includes a capacitor and a transfer field effect transistor coupled between said capacitor and associated one of said bit line and having a gate coupled to associated one of said word lines.

Claim 5

The memory circuit according to claim 1, in which said noise preventing circuit is coupled to one ends of said first and second word lines with the other ends being coupled to said first and second decoders, respectively.

Claim 6

A memory circuit comprising first and second word line groups each including a plurality of word lines arranged in parallel, a plurality of bit lines intersecting with said word lines, a plurality of memory cells each coupled to one of said word lines and one of said bit lines, first and second decoders provided for said first and second word line groups, respectively, a first selection circuit coupled between said first decoder and the word lines of said first word line group, said first selection circuit selecting one of word lines of said first word line group when an output of said first decoder is selected, a second selection circuit coupled between said second decoder and the word lines of said second word line group, said second selection circuit selecting one of word lines of said second word line group when an output of said second decoder is selected, and a cross-coupled circuit connected to adjacent two word lines of said first and second word lines groups one by one, said cross-coupled circuit including a first field effect transistor coupled between one of said adjacent two word lines and a reference voltage, means for connecting a gate of said first transistor to the other of said adjacent two word lines, a second field effect transistor coupled between the other of said adjacent two word lines and said reference voltage, and means for connecting a gate of said second transistor to said one of said adjacent two word lines.

Claim 7

A memory circuit comprising first and second word line groups each including a plurality of word lines arranged in parallel, a plurality of bit lines intersecting with said word lines, a plurality of memory cells each coupled to one of said word lines and one of said bit lines, first and second decoders provided for said first and second word line groups, respectively, a first selection circuit coupled between said first decoder and the word lines of said first word line group, said first selection circuit selecting one of word lines of said first word line group when an output of said first decoder is selected, a second selection circuit coupled between said second decoder and the word lines of said second word line group, said second selection circuit selecting one of word lines of said second word line group when an output of said second decoder is selected, and a cross-coupled circuit connected to adjacent two word lines of said first and second word lines groups one by one, said cross-coupled circuit including a first field effect transistor coupled between one of said adjacent two word lines and a reference voltage, means for connecting a gate of said first transistor to the other of said adjacent two word lines, a second field effect transistor coupled between the other of said adjacent two word lines and said reference voltage, and means for connecting a gate of said second transistor to said one of said adjacent two word lines.

Claim 8

The memory circuit according to claim 5, in which each of decoders is of a dynamic type.

Claim 9

The memory circuit according to claim 5, in which each of said selection circuits includes a plurality of control terminals of the same number as that of the word lines of said word line group, a plurality of selection field effect transistors each coupled between associated one of said control terminals and associated one of the word lines of the associated word line group, and means for connecting gates of said selection transistors to the output of the associated decoder.

Claim 10

The memory circuit according to claim 5, in which said memory cells are arranged in such a manner that every two memory cells connected to adjacent two word lines are connected to the same bit line.

Claim 11

A memory circuit comprising at least two word lines adjacently arranged in parallel, a plurality of bit lines intersecting with said word lines, a plurality of memory cells, each of said memory cells being coupled to one of said word lines and one of said bit lines, selecting means for selecting one of said word lines in response to address signals, and a noise preventing circuit coupled to said two adjacent word lines, said noise preventing circuit maintaining a potential at one of said two adjacent word lines at a referecne voltage when the other of said two adjacent word lines is selected by said selecting means.

Claim 12

A memory circuit comprising at least two word lines adjacently arranged in parallel, a plurality of bit lines intersecting with said word lines, a plurality of memory cells, each of said memory cells being coupled to one of said word lines and one of said bit lines, selecting means for selecting one of said word lines in response to address signals, and a noise preventing circuit coupled to said two adjacent word lines, said noise preventing circuit maintaining a potential at one of said two adjacent word lines at a referecne voltage when the other of said two adjacent word lines is selected by said selecting means.

Claim 13

A transistor circuit comprising first and second drive line, driving means coupled to said first and second drive lines for selectively driving one of said first and second drive lines in response to at least one input signal applied to said driving means, a first transistor having a gate connected to said first drive line, a second transistor having a gate connected to said second drive line, and a noise preventing circuit coupled to said first and second drive lines, said noise preventing circuit including a third transistor coupled between said first drive line and a reference voltage terminal with its drain-source current path, a fourth transistor coupled between said second drive line and said reference voltage terminal, means for connecting a gate of said third transistor to said second drive line and means for connecting a gate of said fourth transistor to said first drive line.

Claim 14

A transistor circuit comprising first and second drive line, driving means coupled to said first and second drive lines for selectively driving one of said first and second drive lines in response to at least one input signal applied to said driving means, a first transistor having a gate connected to said first drive line, a second transistor having a gate connected to said second drive line, and a noise preventing circuit coupled to said first and second drive lines, said noise preventing circuit including a third transistor coupled between said first drive line and a reference voltage terminal with its drain-source current path, a fourth transistor coupled between said second drive line and said reference voltage terminal, means for connecting a gate of said third transistor to said second drive line and means for connecting a gate of said fourth transistor to said first drive line.

Claim 15

The circuit according to claim 10, in which said first and second drive lines are arranged in parallel.