Patent US5281861A successfully refreshed from Google Patents.
US5281861A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sine wave clock distribution with high voltage output
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-03-19
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Granted: 1994-01-25
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Expires: 2012-03-19
Abstract
Abstract A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.
Inventors
- 👤 Thanh T. Tran
- 👤 Clarence Y. Mar
- 👤 Javier F. Izquierdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:46
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
167 words
A method for distributing a clock signal in a digital computer system to an element which uses a square wave clock signal provided to a clock signal input, comprising the steps of; developing on a first circuit board a sine wave signal having a frequency of the desired clock signal; conducting on said first circuit board said sine wave signal to a first connector mounted on said first circuit board; conducting said sine wave signal form a second connector mounted on a second circuit board to a location near the element which uses the square wave clock signal, said second connector removably engageable with said first connector; conducting said sine wave signal from said first connector to said second connector when said connectors are engaged; converting said conducted sine wave signal into a square wave signal having the same frequency as said conducted sine wave signal; and conducting said square wave signal to the clock signal input of the element which uses the square wave clock signal.
Claim 2
Independent Claim
167 words
A method for distributing a clock signal in a digital computer system to an element which uses a square wave clock signal provided to a clock signal input, comprising the steps of; developing on a first circuit board a sine wave signal having a frequency of the desired clock signal; conducting on said first circuit board said sine wave signal to a first connector mounted on said first circuit board; conducting said sine wave signal form a second connector mounted on a second circuit board to a location near the element which uses the square wave clock signal, said second connector removably engageable with said first connector; conducting said sine wave signal from said first connector to said second connector when said connectors are engaged; converting said conducted sine wave signal into a square wave signal having the same frequency as said conducted sine wave signal; and conducting said square wave signal to the clock signal input of the element which uses the square wave clock signal.
Claim 3
Dependent Claim
29 words
The method of claim 1, further comprising: removing any direct current level from said conducted sine wave signal before converting said sine wave signal to said square wave signal.
Claim 4
Dependent Claim
92 words
The method of claim 1, the digital computer system including a plurality of elements which use a square wave clock signal provided to a clock signal input, wherein said steps of converting said conducted sine wave signal into said square wave signal and conducting said square wave signal to the clock signal input of the element which uses the square wave clock signal are repeated for each of the plurality of elements which use the square wave clock signal, whereby each of the plurality of elements receives a repeated square wave signal.
Claim 5
Dependent Claim
277 words
A digital logic system, comprising: a first circuit board; first circuitry on said first circuit board having a square wave clock signal input for receiving a square wave signal of a desired frequency; a second circuit board; means for developing and outputting a sine wave signal having a frequency of the desired square wave signal frequency, said developing and outputting means located on said second circuit board; a first connector mounted on said second circuit board; means for conducting on said second circuit board said sine wave signal from said means for developing and outputting said sine wave signal to said first connector; a second connector mounted on said first circuit board, said first and second connectors being removably mateable; means for conducting said sine wave signal from said first connector to said second connector when said first and second connectors are mated; means for conducting said sine wave signal on said first circuit board from said second connector to a location near said first circuitry receiving said square wave signal from said second connector; means for receiving said conducted sine wave signal from said second connector and for converting said conducted sine wave signal into a square wave signal having the same frequency as said sine wave signal and outputting said square wave signal, wherein said means for receiving said conducted sine wave signal and for converting said conducted sine wave signal is located on said first circuit board near said circuitry receiving said square wave signal; and means for conducting on said first circuit board said output square wave signal from said receiving and converting means to said first circuitry square wave clock signal input.
Claim 6
Dependent Claim
277 words
A digital logic system, comprising: a first circuit board; first circuitry on said first circuit board having a square wave clock signal input for receiving a square wave signal of a desired frequency; a second circuit board; means for developing and outputting a sine wave signal having a frequency of the desired square wave signal frequency, said developing and outputting means located on said second circuit board; a first connector mounted on said second circuit board; means for conducting on said second circuit board said sine wave signal from said means for developing and outputting said sine wave signal to said first connector; a second connector mounted on said first circuit board, said first and second connectors being removably mateable; means for conducting said sine wave signal from said first connector to said second connector when said first and second connectors are mated; means for conducting said sine wave signal on said first circuit board from said second connector to a location near said first circuitry receiving said square wave signal from said second connector; means for receiving said conducted sine wave signal from said second connector and for converting said conducted sine wave signal into a square wave signal having the same frequency as said sine wave signal and outputting said square wave signal, wherein said means for receiving said conducted sine wave signal and for converting said conducted sine wave signal is located on said first circuit board near said circuitry receiving said square wave signal; and means for conducting on said first circuit board said output square wave signal from said receiving and converting means to said first circuitry square wave clock signal input.
Claim 7
Dependent Claim
30 words
The digital logic system of claim 4, wherein said converting means includes means for removing direct current components from said sine wave signal prior to converting said sine wave signal.
Claim 8
Dependent Claim
103 words
The digital logic system of claim 4, further comprising; second circuitry on said second circuit board having a square wave clock signal input for receiving a square wave signal of said desired frequency; means for conducting said sine wave signal to a location near said second circuitry; means for receiving said conducted sine wave signal and for converting said conducted sine wave signal into a second square wave signal having the same frequency as said sine wave signal and outputting said second square signal; and means for conducting said second output square wave signal to said second circuitry square wave clock signal input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |