US4728815A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data shaping circuit
Assignee: NXP USA Inc
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Filing: 1986-10-16
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Granted: 1988-03-01
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Expires: 2006-10-16
Abstract
Abstract A circuit for producing output pulses in response to an alternating signal supplied to the input thereof which is comprised of a pair of complementary transistors cascoded between a pair of current mirror circuits which source and sink currents to and from a common terminal respectively. The alternating input signal is applied to the interconnected emitters of the two transistors thereby rendering one more conductive while the other is rendered less conductive and vice versa. The currents which are sourced or sunk at the common terminal are proportional to the currents flowing in the two transistors and are compared to cause an output transistor to switch operating states thereby producing the output pulse.
Inventors
- 👤 W. Eric Main
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:43
CPC Classifications
H; H04; H04L; H04L27/00; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666; H03K17/667; H03K5/00; H03K5/01; H03K5/08
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
309 words
A data shaping circuit responsive to an alternating input signal supplied to an input thereof through a capacitive element for producing a rectangular output pulse at an output, comprising: first circuit means responsive to the alternating signal for providing current drive, said first cirucit means including a first semiconductor PN junction having a first electrode coupled to the input which is forward biased by the alternating input signal during its positive half cycle to provide current flow therethrough and a second semiconductor PN junction having a first electrode coupled to the input which is forward biased by the alternating input signal during its negative half cycle to provide current flow therethrough; means for providing biasing to said first and second semiconductor PN junctions in a quiescent operating state; second circuit means coupled to said first and said second semiconductor PN junctions which is responsive to said currents flowing in said first and second semiconductor PN junctions for providing the output pulse, the output pulse being at a first level when said current flow in said first semiconductor PN junction is greater than said current flow in said second semiconductor PN junction and being at a second level when said current flow in said first semiconductor PN junction is less than said current flow in said second semiconducotr PN junction; said first semiconductor PN junction is a first transistor the base-emitter path being coupled between a first output terminal of said bias circuit and the input of the data shaping circuit and its collector being coupled to said second circuit means; and said second semiconductor PN junction is a second transistor of opposite conductivity type from said first transistor the base-emitter path being coupled between a second output of said bias circuit and the input of the data shaping circuit and its collector being coupled to said second circuit means.
Claim 2
Dependent Claim
309 words
A data shaping circuit responsive to an alternating input signal supplied to an input thereof through a capacitive element for producing a rectangular output pulse at an output, comprising: first circuit means responsive to the alternating signal for providing current drive, said first cirucit means including a first semiconductor PN junction having a first electrode coupled to the input which is forward biased by the alternating input signal during its positive half cycle to provide current flow therethrough and a second semiconductor PN junction having a first electrode coupled to the input which is forward biased by the alternating input signal during its negative half cycle to provide current flow therethrough; means for providing biasing to said first and second semiconductor PN junctions in a quiescent operating state; second circuit means coupled to said first and said second semiconductor PN junctions which is responsive to said currents flowing in said first and second semiconductor PN junctions for providing the output pulse, the output pulse being at a first level when said current flow in said first semiconductor PN junction is greater than said current flow in said second semiconductor PN junction and being at a second level when said current flow in said first semiconductor PN junction is less than said current flow in said second semiconducotr PN junction; said first semiconductor PN junction is a first transistor the base-emitter path being coupled between a first output terminal of said bias circuit and the input of the data shaping circuit and its collector being coupled to said second circuit means; and said second semiconductor PN junction is a second transistor of opposite conductivity type from said first transistor the base-emitter path being coupled between a second output of said bias circuit and the input of the data shaping circuit and its collector being coupled to said second circuit means.
Claim 3
Dependent Claim
88 words
The circuit of claim 1 wherein said second circuit means includes: current mirror circuitry responsive to current flowing in said first transistor for sourcing a proportional current to a first circuit node and being responsive to current flowing in said second transistor for sinking proportional current from said first circuit node; and switching circuit means having an input coupled to said first circuit node and an output coupled to the output of the data shaping circuit for producing the output pulse in response to said current mirror circuitry.
Claim 4
Dependent Claim
62 words
The circuit of claim 2 wherein said current mirror circuitry includes: a first current mirror circuit having an input coupled to said collector of said first transistor and an output coupled to said first circuit node; and a second current mirror circuit having an input coupled to said collector of said second transistor and an output coupled to said first circuit node.
Claim 5
Dependent Claim
52 words
The circuit of claim 3 wherein said bias circuit includes: a third transistor having an emitter, collector and base; resistive means for coupling said collector and emitter of said third transistor between first and second power supply conductors; and means for supplying base current drive to said base of said third transistor.
Claim 6
Dependent Claim
81 words
The circuit of claim 4 wherein said means for supplying base current includes: a fourth transistor having an emitter, collector and base, said emitter being coupled to said collector of said third transistor, said collector being coupled to said base of said third transistor; and a fifth transistor having an emitter, a collector and a base, said collector and base being coupled to said base of said fourth transistor and said emitter being coupled to said emitter of said third transistor.
Claim 7
Dependent Claim
42 words
The circuit of claim 4 wherein said means for supplying base current drive includes a fourth transistor the base and collector being coupled to said base of said third transistor and the emitter being coupled to said collector of said third transistor.
Claim 8
Dependent Claim
255 words
A data shaping circuit responsive to an alternating input signal supplied to an input thereof through a capacitive element for producing a rectangular output pulse at an output, comprising: first circuit responsive to the alternating signal for providing current drive, said first circuit means including a first semiconductor PN junction having a first electrode coupled to the input which is forward biased by the alternating input signal during its positive half cycle to provide current flow therethrough and a second semiconductor PN junction having a first electrode coupled to the input which is forward biased by the alternating input signal during its negative half cycle to provide current flow therethrough; means for providing biasing to said first and second semiconductor PN junctions in a quiescent operating state; second circuit means coupled to said first and said second semiconductor PN junctions which is responsive to said currents flowing in said first and second semiconductor PN junctions for providing the output pulse, the output pulse being at a first level when said current flow in said first semiconductor PN junction is greater than said current flow in said second semiconductor PN junction and being at a second level when said current flow in said first PN junction is less than said current flow in said second semiconductor PN junction; said second circuit means includes a comparator having a first input coupled to the input of the circuit, and second input coupled to said source of biasing potential and an output coupled to the output of the circuit.
Claim 9
Dependent Claim
255 words
A data shaping circuit responsive to an alternating input signal supplied to an input thereof through a capacitive element for producing a rectangular output pulse at an output, comprising: first circuit responsive to the alternating signal for providing current drive, said first circuit means including a first semiconductor PN junction having a first electrode coupled to the input which is forward biased by the alternating input signal during its positive half cycle to provide current flow therethrough and a second semiconductor PN junction having a first electrode coupled to the input which is forward biased by the alternating input signal during its negative half cycle to provide current flow therethrough; means for providing biasing to said first and second semiconductor PN junctions in a quiescent operating state; second circuit means coupled to said first and said second semiconductor PN junctions which is responsive to said currents flowing in said first and second semiconductor PN junctions for providing the output pulse, the output pulse being at a first level when said current flow in said first semiconductor PN junction is greater than said current flow in said second semiconductor PN junction and being at a second level when said current flow in said first PN junction is less than said current flow in said second semiconductor PN junction; said second circuit means includes a comparator having a first input coupled to the input of the circuit, and second input coupled to said source of biasing potential and an output coupled to the output of the circuit.
Claim 10
Dependent Claim
65 words
The circuit of claim 7 wherein said first semiconductor PN junction is a first diode having an anode coupled to the input of the circuit and a cathode coupled to said source of bias potential and said second semiconductor PN junction is a second diode having an anode coupled to said source of bias potential and a cathode coupled to the input of the circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-01 | 1991-08-31 | 1992-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-01 | 1995-08-31 | 1996-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-01 | 1999-08-31 | 2000-03-01 | $7700.00 | Window Closed / Lapsed |