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US5281837A
Expired / Lapsed
US
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Semiconductor memory device having cross-point DRAM cell structure
Assignee: Toshiba Corp
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Filing: 1991-05-23
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Granted: 1994-01-25
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Expires: 2011-05-23
Abstract
Abstract For providing a semiconductor memory device that includes a plurality of cross-point memory cells each having a fine device structure and a high capacitance, a bit line is formed on an insulating substrate, and a word line is disposed above the substrate so as to cross the bit line. A MOS transistor with a vertical structure, whose gate electrode is used as the word line, is provided on the bit line. A MIM (Metal-Insulator-Metal) capacitor is provided on the MOS transistor.
Inventors
- 👤 Yusuke Kohyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318; H10B12/39; H10B12/395; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
148 words
A cross-point memory cell in a semiconductor memory device comprising: a substrate; a bit line provided on said substrate; a first insulating film provided over said substrate to cover said bit line; a semiconductor layer provided over said first insulating film to define a MOS transistor, said MOS transistor having source and drain regions and a gate electrode covered with a gate insulating film said gate electrode being used as a word line and crossing said bit line, one of said source and drain regions being coupled to said bit line through a first aperture formed in said first insulating film; a second insulating film provided over said semiconductor layer; and an MIM capacitor provided on said second insulating film so as to be coupled to the other of said source and drain regions of said MOS transistor through a second aperture formed in said second insulating film.
Claim 2
Dependent Claim
148 words
A cross-point memory cell in a semiconductor memory device comprising: a substrate; a bit line provided on said substrate; a first insulating film provided over said substrate to cover said bit line; a semiconductor layer provided over said first insulating film to define a MOS transistor, said MOS transistor having source and drain regions and a gate electrode covered with a gate insulating film said gate electrode being used as a word line and crossing said bit line, one of said source and drain regions being coupled to said bit line through a first aperture formed in said first insulating film; a second insulating film provided over said semiconductor layer; and an MIM capacitor provided on said second insulating film so as to be coupled to the other of said source and drain regions of said MOS transistor through a second aperture formed in said second insulating film.
Claim 3
Dependent Claim
18 words
The cross-point memory cell according to claim 1, wherein said word line is buried in said semiconductor layer.
Claim 4
Dependent Claim
163 words
A cross-point memory cell in a semiconductor memory device comprising: a first memory cell including one conductivity type semiconductor substrate, a trench type capacitor provided in said semiconductor substrate, a first MOS transistor with a vertical structure provided on said trench type capacitor, said first MOS transistor having a first gate electrode used as a first word line, and a first bit line provided on said first MOS transistor, said first bit line crossing said first word line; and a second memory cell stacked above said first memory cell through an interlevel insulator, said second memory cell including a second bit line provided on said interlevel insulator, a second word line disposed above said interlevel insulator so as to cross said second bit line, a second MOS transistor with a vertical structure provided on said second bit line, said second MOS transistor having a second gate electrode used as said second word line, and an MIM capacitor provided on said second MOS transistor.
Claim 5
Dependent Claim
163 words
A cross-point memory cell in a semiconductor memory device comprising: a first memory cell including one conductivity type semiconductor substrate, a trench type capacitor provided in said semiconductor substrate, a first MOS transistor with a vertical structure provided on said trench type capacitor, said first MOS transistor having a first gate electrode used as a first word line, and a first bit line provided on said first MOS transistor, said first bit line crossing said first word line; and a second memory cell stacked above said first memory cell through an interlevel insulator, said second memory cell including a second bit line provided on said interlevel insulator, a second word line disposed above said interlevel insulator so as to cross said second bit line, a second MOS transistor with a vertical structure provided on said second bit line, said second MOS transistor having a second gate electrode used as said second word line, and an MIM capacitor provided on said second MOS transistor.
Claim 6
Dependent Claim
26 words
The cross point memory cell according to claim 3, wherein said first memory cell is electrically insulated from said second memory cell through said interlevel insulator.
Claim 7
Dependent Claim
24 words
The cross point memory cell according to claim 3, wherein said first word line and said second word line extend in a same direction.
Claim 8
Dependent Claim
24 words
The cross point memory cell according to claim 3, wherein said first bit line and said second bit line extend in a same direction.
Claim 9
Dependent Claim
23 words
The cross point memory cell according to claim 3, wherein said first bit line faces said second bit line through said interlevel insulator.
Claim 10
Dependent Claim
50 words
The cross-point memory cell according to claim 3, wherein said MIM capacitor includes a storage node electrode connected to one of source and drain regions of said second MOS transistor, an insulating film covering a surface of said storage node electrode, and a cell plate electrode covering said insulating film.
Claim 11
Dependent Claim
39 words
The cross-point memory cell according to claim 8, wherein said insulating film of said MIM capacitor is comprised of an insulating material selected from SiO 2 , Si 3 N 4 , Ta 2 O 5 , and PZTs.
Claim 12
Dependent Claim
20 words
The cross-point memory cell according to claim 8, wherein said insulating film of said MIM capacitor has a multilayer structure.
Claim 13
Dependent Claim
19 words
The cross-point memory cell according to claim 10, wherein said multilayer structure includes a high dielectric constant insulating film.
References Cited (Backward Citations)
US3305394A
Cited
US4984038A
Cited
US4630088A
Cited
JPS63172458A
Cited
JPS6425462A
Cited
JPS6425466A
Cited
JPS6425461A
Cited
JPH0191449A
Cited
JPH0191450A
Cited
US4970564A
Cited
US4974060A
Cited
US4882649A
Cited
JPH01307260A
Cited
JPH02159058A
Cited
US5136534A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |