US4984038A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory and method of producing the same
Assignee: Hitachi Ltd
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Filing: 1988-05-17
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Granted: 1991-01-08
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Expires: 2008-05-17
Abstract
Abstract The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.
Inventors
- 👤 Hideo Sunami
- 👤 Makoto Ohkura
- 👤 Masanobu Miyao
- 👤 Kikuo Kusukawa
- 👤 Masahiro Moniwa
- 👤 Shinichiro Kimura
- 👤 Terunori Warabisako
- 👤 Tokuo Kure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:04
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
180 words
A semiconductor random access memory formed on a semiconductor substrate, said random access memory having a plurality of memory cells which each comprise: a capacitor including a capacitor node formed in a groove formed in the substrate, a capacitor plate formed as a portion of the substrate, and a capacitor dielectric film isolating said capacitor plate from said capacitor node; and a field effect transistor at least partially formed over said capacitor node, said field effect transistor including a semiconductor portion formed over said capacitor node, wherein a bit line is coupled to a source-drain path of said field effect transistor, wherein a word line is respectively coupled to said field effect transistor to serve as a gate electrode for the field effect transistor between said bit line and said capacitor node, wherein applying a predetermined voltage to said word line increases a channel between said capacitor node and said bit line to connect said capacitor node to said bit line, and wherein said channel extends vertically in substantially a straight line between said capacitor node and said bit line.
Claim 2
Dependent Claim
180 words
A semiconductor random access memory formed on a semiconductor substrate, said random access memory having a plurality of memory cells which each comprise: a capacitor including a capacitor node formed in a groove formed in the substrate, a capacitor plate formed as a portion of the substrate, and a capacitor dielectric film isolating said capacitor plate from said capacitor node; and a field effect transistor at least partially formed over said capacitor node, said field effect transistor including a semiconductor portion formed over said capacitor node, wherein a bit line is coupled to a source-drain path of said field effect transistor, wherein a word line is respectively coupled to said field effect transistor to serve as a gate electrode for the field effect transistor between said bit line and said capacitor node, wherein applying a predetermined voltage to said word line increases a channel between said capacitor node and said bit line to connect said capacitor node to said bit line, and wherein said channel extends vertically in substantially a straight line between said capacitor node and said bit line.
Claim 3
Dependent Claim
48 words
A semiconductor random access memory device structure according to claim 1, wherein the capacitor dielectric film is formed of a material selected from a group comprised of SiO 2 , Si 3 N 4 , Ta 2 O 5 , Ti 2 O 5 and GrO 2 .
Claim 4
Dependent Claim
51 words
A semiconductor random access memory device structure according to claim 2, wherein the field effect transistor is a metal-oxide-semiconductor field effect transistor and wherein the word lines are formed of a material selected from a group comprised of polycrystalized silicon, W, Mo, WSi 2 , MoSi 2 and TiSi 2 .
Claim 5
Dependent Claim
141 words
A semiconductor random access memory according to claim 1, wherein said semiconductor portion has a bottom surface contacting an upper surface of said capacitor node, a side surface and an upper surface opposed to said bottom surface, wherein a region is formed in said upper surface of said semiconductor portion as one of a source or drain of said field effect transistor, wherein said bit line is formed on said region, wherein a gate insulating film is formed on said side surface of said semiconductor portion, wherein said gate electrode is formed over said gate insulating film to be separated from said side surface of said semiconductor portion, and wherein applying a predetermined voltage to said gate electrode increases a channel in said semiconductor portion between said region and said capacitor node to connect said capacitor node to said bit line.
Claim 6
Dependent Claim
26 words
A semiconductor random access memory according to claim 1, wherein said capacitor dielectric film comprises at least two insulating layers of different material from one another.
Claim 7
Dependent Claim
24 words
A semiconductor random access memory according to claim 1, wherein said capacitor plate includes a side wall portion of said groove in said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-01-07 | 1994-07-09 | 1995-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-07 | 1998-07-09 | 1999-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-07 | 2002-07-09 | 2003-01-08 | $7700.00 | Window Closed / Lapsed |