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US5280203A
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Look-ahead asynchronous register set/reset in programmable logic device
Assignee: Altera Corp
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Filing: 1992-05-15
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Granted: 1994-01-18
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Expires: 2012-05-15
Abstract
Abstract A programmable logic device in which macrocell register reset time, T clear , and set time, T set , are comparable in speed to the combinatorial propagation delay time, T pd . In setting or resetting the macrocell register, the Set (Reset) signal is applied simultaneously to a clocked master latch in the macrocell register and to an output node. During the Set (Reset) period the slave latch of the macrocell register is disconnected from the output node.
Inventors
- 👤 Chuan-Yung Hung
- 👤 Ray-Lin Wan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/1774; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
94 words
In a programmable logic device having a macrocell register including master and slave latches for connecting a combinatorial output to an output node, reset circuitry for asynchronously resetting said macrocell register and said output node comprising: first means responsive to a reset signal for applying a logic "0" voltage potential to an input to said master latch, and second means responsive to said reset signal for simultaneously applying a logic "0" voltage potential directly to said output node, thereby providing look-ahead resetting of said output node while said master and slave latches are resetting.
Claim 2
Dependent Claim
94 words
In a programmable logic device having a macrocell register including master and slave latches for connecting a combinatorial output to an output node, reset circuitry for asynchronously resetting said macrocell register and said output node comprising: first means responsive to a reset signal for applying a logic "0" voltage potential to an input to said master latch, and second means responsive to said reset signal for simultaneously applying a logic "0" voltage potential directly to said output node, thereby providing look-ahead resetting of said output node while said master and slave latches are resetting.
Claim 3
Dependent Claim
37 words
The reset circuitry as defined by claim 1 wherein said first means includes a field effect transistor connected between a logic "0" voltage potential and said master latch and having a gate for receiving said reset signal.
Claim 4
Dependent Claim
37 words
The reset circuitry as defined by claim 2 wherein said second means includes a field effect transistor connected between a logic "0" voltage potential and said output node and having a gate for receiving said reset signal.
Claim 5
Dependent Claim
79 words
Circuitry as defined by claim 3 and further including set circuitry for asynchronously setting said macrocell and said output node comprising third means responsive to a set signal for applying a logic "0" voltage potential to an output of said master latch, and fourth means responsive to said set signal for simultaneously applying a logic "1" voltage potential directly to said output node, thereby providing look-ahead setting of said output node while said master and slave latches are setting.
Claim 6
Dependent Claim
35 words
Circuitry as defined by claim 4 wherein said third means comprises a field effect transistor connected between a logic "0" voltage potential and said master latch and having a gate for receiving said set signal.
Claim 7
Dependent Claim
46 words
Circuitry as defined by claim 5 wherein said fourth means comprises a field effect transistor connected between a logic "1" voltage potential and said output node and having a gate responsive to said set signal for applying a logic "1" voltage potential to said output node.
Claim 8
Dependent Claim
62 words
Circuitry as defined by claim 1 and further including set circuitry for asynchronously setting said macrocell and said output node comprising: third means responsive to a set signal for applying a logic "0" voltage potential to an output of said master latch, and fourth means responsive to said set signal for simultaneously applying a logic "1" voltage potential to said output node.
Claim 9
Dependent Claim
143 words
Output circuitry for a programmable logic device having a combinatorial output and a reset, said circuit comprising: a register including a master latch, a slave latch, and a first transmission gate serially connecting said master latch and said slave latch, an output node, a second transmission gate connecting said slave latch and said output node, a third transmission gate connecting said combinatorial output to said master latch, a fourth transmission gate connecting said combinatorial output to said output node, first means responsive to a reset signal for applying a logic "0" voltage potential to an input to said master latch, and second means responsive to said reset signal for simultaneously applying a logic "0" voltage potential directly to said output node for asynchronously resetting said combinatorial output, thereby providing look-ahead resetting of said output node while said master and slave latches are resetting.
Claim 10
Dependent Claim
143 words
Output circuitry for a programmable logic device having a combinatorial output and a reset, said circuit comprising: a register including a master latch, a slave latch, and a first transmission gate serially connecting said master latch and said slave latch, an output node, a second transmission gate connecting said slave latch and said output node, a third transmission gate connecting said combinatorial output to said master latch, a fourth transmission gate connecting said combinatorial output to said output node, first means responsive to a reset signal for applying a logic "0" voltage potential to an input to said master latch, and second means responsive to said reset signal for simultaneously applying a logic "0" voltage potential directly to said output node for asynchronously resetting said combinatorial output, thereby providing look-ahead resetting of said output node while said master and slave latches are resetting.
Claim 11
Dependent Claim
63 words
Circuitry as defined by claim 8 wherein said first means includes a field effect transistor connected between a logic "0" voltage potential and said master latch and having a gate for receiving said reset signal, said second means including a field effect transistor connected between a logic "0" voltage potential and said output node and having a gate for receiving said reset signal.
Claim 12
Dependent Claim
77 words
Circuitry as defined by claim 8 and further including set circuitry for asynchronously setting said macrocell and said output node comprising third means responsive to a set signal for applying a logic "0" to an output of said master latch, and fourth means responsive to said set signal for simultaneously applying a logic "1" voltage potential directly to said output node, thereby providing look-ahead setting of said output node while said master and slave latches are setting.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-17 | 1997-07-19 | 1998-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-17 | 2001-07-19 | 2002-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-17 | 2005-07-19 | 2006-01-18 | $7700.00 | Window Closed / Lapsed |