Method of marking a lateral mos controlled thyristor

Claim 1

A method of making a lateral MOS controlled thyristor in a epitaxial layer (20) having a first conductivity type, characterized by the steps of: forming a first region (11), of a second conductivity type, in the major surface of the epitaxial layer, the second conductivity type being opposite that of the first conductivity type; forming a second region (12), of the second conductivity type and having a resistivity, in the major surface of the epitaxial layer and spaced apart from the first region; forming a third region (13), of the first conductivity type, within the first region; forming a fourth region (14), of the second conductivity type having a resistivity greater than the resistivity of the second region, adjacent to, and in contact with, the second region; forming a rectifying contact to the second region; forming an additional region (16) of the first conductivity type in the major surface such that the first region is between the fifth and fourth regions; forming a single conductive layer (17) overlaying, and insulated from, the major surface of the epitaxial layer between the third region and the fourth region and overlaying the major surface of the epitaxial layer and the first region between the third and additional regions, so as to create a turn-on transistor defined by the combination of the conductive layer, the first region, and the fourth region, a turn-off transistor defined by the combination of the conductive layer, third region, and the epitaxial layer, and an additional turn-off transistor defined by the combination of the conductive layer, the third region, and the additional region; and, contacting the first and third regions to form a first output terminal of the thyristor; wherein the rectifying contact to the second region is a second output terminal and the conductive layer is the gate of the thyristor.

Claim 2

A method of making a lateral MOS controlled thyristor in a epitaxial layer (20) having a first conductivity type, characterized by the steps of: forming a first region (11), of a second conductivity type, in the major surface of the epitaxial layer, the second conductivity type being opposite that of the first conductivity type; forming a second region (12), of the second conductivity type and having a resistivity, in the major surface of the epitaxial layer and spaced apart from the first region; forming a third region (13), of the first conductivity type, within the first region; forming a fourth region (14), of the second conductivity type having a resistivity greater than the resistivity of the second region, adjacent to, and in contact with, the second region; forming a rectifying contact to the second region; forming an additional region (16) of the first conductivity type in the major surface such that the first region is between the fifth and fourth regions; forming a single conductive layer (17) overlaying, and insulated from, the major surface of the epitaxial layer between the third region and the fourth region and overlaying the major surface of the epitaxial layer and the first region between the third and additional regions, so as to create a turn-on transistor defined by the combination of the conductive layer, the first region, and the fourth region, a turn-off transistor defined by the combination of the conductive layer, third region, and the epitaxial layer, and an additional turn-off transistor defined by the combination of the conductive layer, the third region, and the additional region; and, contacting the first and third regions to form a first output terminal of the thyristor; wherein the rectifying contact to the second region is a second output terminal and the conductive layer is the gate of the thyristor.