Patent US5276400A successfully refreshed from Google Patents.
US5276400A
Expired / Lapsed
US
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Test circuit for imaging sensing integrated circuits
Assignee: VLSI Vision Ltd
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Filing: 1990-09-20
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Granted: 1994-01-04
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Expires: 2010-09-20
Abstract
Abstract The design and testing of integrated circuits in wafer form for production faults, in the absence of irradiation, is described. This is achieved by fabricating test circuits on each wafer at the periphery of the sensor array. In a preferred arrangement, two test circuits are fabricated on each wafer; one for testing the word lines and the other for testing the bit lines and individual sensing sites. The test circuits are controlled by external signals to input predetermined patterns of data to the array and the array output patterns are compared with the input patterns to assess the level of production faults.
Inventors
- 👤 Peter B. Denyer
- 👤 David Renshaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:46
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/277; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; H04; H04N; H04N25/00; H04N25/60; H04N25/68; H04N25/69; H04N25/70; H04N25/71; H04N25/74; H04N25/76
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
184 words
An image sensing integrated circuit (IC) having a sensor array comprising a multiplicity of radiation sensing sites, a plurality of word-lines and a plurality of bit-lines, each sensing site being capable of storing an analog charge packet for a predetermined period, said sensor array being coupled on-board to signal read-out means for providing an output signal from said sensor array, said sensor array being coupled to on-board digital test circuit means disposed at the periphery of the array, said on-board digital...test circuit means being responsive to a control signal to generate a digital test signal for testing the integrity of at least one of a plurality of the sensor array bit-lines and a plurality of the sensor array word-lines in the absence of test irradiation on said sensing sites, and on-board monitoring and read-out means coupled to said sensor array for monitoring an output signal from said sensor array corresponding to said digital test signal to output the detected states of the word-lines, bit-lines or individual sensing sites to identify the level of production faults in said IC in the absence of test irradiation.
Claim 2
Dependent Claim
184 words
An image sensing integrated circuit (IC) having a sensor array comprising a multiplicity of radiation sensing sites, a plurality of word-lines and a plurality of bit-lines, each sensing site being capable of storing an analog charge packet for a predetermined period, said sensor array being coupled on-board to signal read-out means for providing an output signal from said sensor array, said sensor array being coupled to on-board digital test circuit means disposed at the periphery of the array, said on-board digital...test circuit means being responsive to a control signal to generate a digital test signal for testing the integrity of at least one of a plurality of the sensor array bit-lines and a plurality of the sensor array word-lines in the absence of test irradiation on said sensing sites, and on-board monitoring and read-out means coupled to said sensor array for monitoring an output signal from said sensor array corresponding to said digital test signal to output the detected states of the word-lines, bit-lines or individual sensing sites to identify the level of production faults in said IC in the absence of test irradiation.
Claim 3
Dependent Claim
42 words
An IC as claimed in claim 1 including comparison means coupled to said on-board monitoring means for comparing said output signal with an input signal to identify the level of production faults in said integrated circuit in the absence of test irradiation.
Claim 4
Dependent Claim
55 words
An IC as claimed in claim 1, wherein said digital test circuit means comprises a first test circuit located at the periphery of the array for testing the integrity of the sensor array bit-lines and a second test circuit located at the periphery of the array for testing the integrity of the sensor array word-lines.
Claim 5
Dependent Claim
23 words
An IC as claimed in claim 3, wherein said first digital test circuit includes means for testing the integrity of individual sensing sites.
Claim 6
Dependent Claim
20 words
An IC as claimed in claim 3 wherein said first and said second test circuits are implemented by shift registers.
Claim 7
Dependent Claim
28 words
An IC as claimed in claim 3 wherein said integrated circuit is implemented in one of CMOS, MOS, NMOS, PMOS, BIMOS, BICMOS, Bipolar and amorphous silicon manufacturing technologies.
Claim 8
Independent Claim
140 words
A method of testing image array sensors at the wafer stage for manufacturing faults, said method comprising the steps of, fabricating said wafer with on-board digital test circuit means located at the periphery of the array, coupling said on-board digital test circuit means to an external signal source, in response to a signal from said external test signal source generating a predetermined input digital test signal from said on-board digital test circuit means, applying said predetermined digital test signal to at least one of a plurality of sensor array bit-lines and a plurality of sensor array word-lines of said sensor array, monitoring an output signal from said sensor array corresponding to said predetermined digital test signal and comparing the input and output signals to identify the level of production faults in said integrated circuit in the absence of test irradiation.
Claim 9
Independent Claim
140 words
A method of testing image array sensors at the wafer stage for manufacturing faults, said method comprising the steps of, fabricating said wafer with on-board digital test circuit means located at the periphery of the array, coupling said on-board digital test circuit means to an external signal source, in response to a signal from said external test signal source generating a predetermined input digital test signal from said on-board digital test circuit means, applying said predetermined digital test signal to at least one of a plurality of sensor array bit-lines and a plurality of sensor array word-lines of said sensor array, monitoring an output signal from said sensor array corresponding to said predetermined digital test signal and comparing the input and output signals to identify the level of production faults in said integrated circuit in the absence of test irradiation.
Claim 10
Dependent Claim
84 words
A method as claimed in claim 7, wherein said method includes the step of fabricating a first on-board digital test circuit at the periphery of the array for testing said plurality of sensor array word-lines and fabricating a second on-board digital test circuit at the periphery of the array for testing said plurality of said sensor array bit-lines, and monitoring respective output signals from said first and second test circuits to assess the level of production faults in said word-lines and said bit-lines respectively.
Claim 11
Dependent Claim
32 words
A method as claimed in claim 8, wherein one of said first and second test circuits generates a test signal to test the level of production faults in said individual sensing sites.
Claim 12
Dependent Claim
41 words
A method, as claimed in claim 8, wherein said method includes the step of controlling said test circuit means so as to drive the sensor array in one of a number of different signal patterns to optimise detection of production faults.
References Cited (Backward Citations)
WO1982002603A1
Cited
US4527115A
Cited
WO1984002580A1
Cited
JPS6269671A
Cited
EP0223714A2
Cited
US4843312A
Cited
US4894605A
Cited
US5012185A
Cited
US5057775A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-03 | 1997-07-05 | 1998-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-03 | 2001-07-05 | 2002-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-03 | 2005-07-05 | 2006-01-04 | $7700.00 | Window Closed / Lapsed |