Information processing apparatus having micro instructions stored both in on-chip ROM and off-chip memory

Claim 1

An information processing apparatus comprising: a memory; an address bus coupled to said memory for carrying an address to the memory; a data bus coupled to said memory for carrying data to and from the memory; a fetch pointer connected to the address bus for holding an address of a macro instruction to be read out from the memory; a memory address register (MAR) connected to the access bus for holding an address of an operand to be written into or read from the memory; an instruction buffer connected to the data bus for storing a macro instruction read from the memory; a memory data register (MDR) connected to the data bus for holding an operand to be written into or read from the memory; a micro instruction pointer connected to said address bus for holding a memory address converted from a micro instruction address; a computation unit controlled by a micro instruction for performing a calculation; a micro instruction control unit including a sub micro instruction register (SMIR) connected to the data bus for holding a micro instruction; a micro instruction address register (MIAR) for holding a micro instruction address; a ROM storing a part of a plurality of micro instructions with the remaining part of said plurality of micro instructions being stored in the memory, the ROM being connected to said micro instruction address register and to said sub micro instruction register; next address determining means coupled to said sub micro instruction register for decoding the field of a micro instruction which specifies a next micro instruction of a sequence of micro instructions, and for generating and sending a next micro instruction address to said micro instruction address register; means for detecting from the address of a desired micro instruction stored in said MIAR that the desired micro instruction is not present in the ROM; means for converting the address of a desired micro instruction into a memory address for accessing a storage location in the memory and transferring the memory address to the micro instruction pointer; means for inhibiting micro instruction reading from the ROM, for reading a desired microinstruction from the memory and for storing the read micro instruction in said sub micro instruction register in response to said detecting means; and a memory control unit connected to said fetch pointer, said memory address register, said micro instruction pointer and said micro instruction control unit for controlling the transfer of macro instruction, micro instruction and operand addresses on said address bus.