Data structure processor

Claim 2

Apparatus for use in carrying out data processing operations in which data items are called from storage by an address, the apparatus including a primary store for storing items of data at a plurality of storage locations, the primary store having an address input and each location having a unique real address which when applied to the said address input in the form of a real address allows transfer of data items to and from that location of the primary store, a main store having a greater number of storage locations than the primary store, means for allowing transfer of stored items between the primary and main stores, an address translator, having its output coupled to the address input of the primary store, for translating into real addresses for data items from virtual addresses for said items to allow programs of data processing operations which use virtual addresses to be used, and a program storage means for storing said programs which use virtual addresses, each real address being changeably associated with a virtual address particular thereto, changes in the associations between real and virtual addresses effecting changes in the said programs, and the translator including translator storage means, separate from the primary and main stores, for storing addresses, and conversion means for changing the associations between real and virtual addresses independently of transfer of data items between the main and primary stores, said conversion means including logic means for changing said associations while real addresses of data items remain the same by operating upon addresses already held by the translator storage means, the said changes in associations being carried out by the conversion means in response to instruction signals applied to the conversion means.

Claim 3

Apparatus according to claim 1, wherein the translator storage means includes real-address storage means comprising single-bit stores each of which, in operation, contains one bit of a real address, with different single-bit stores containing bits of different real addresses, and means for decoding virtual addresses, coupled to the single-bit stores to allow the said bits of real addresses to be read from the translator, and wherein the conversion means is constructed to transfer real-address bits from one single-bit store to another in order to change the association between real and virtual addresses.

Claim 4

Apparatus according to claim 1, including further logic means for changing at least one of the bits of a virtual address according to signals applied to the further logic means from said program storage means.

Claim 5

Apparatus according to claim 1 including a secondary store having a relatively short access time in relation to the main store, and means for transferring items of data between the three stores.

Claim 6

Apparatus according to claim 3, wherein the further logic means includes a register for receiving virtual addresses one at a time for application to the translator, and a number of Exclusive-OR circuits coupled to receive the said control signals, and each coupled between one stage of the register and the translator to form a different virtual address from that held by the register by changing a bit of the virtual address held by the register, if the control signals so require, in applying virtual addresses to the translator.

Claim 7

Apparatus according to claim 1, wherein the conversion means includes means for changing at least one of the more significant bits only in virtual addresses to allow the association between a block of virtual and real addresses to be changed, rather than the association between individual words.

Claim 8

Apparatus according to claim 1, wherein the translator storage means includes a number of groups of first bistable circuits, one group associated with each virtual address and one bistable circuit in each group being associated with a bit of predetermined significance in a virtual address, a number of output terminals, a first group of gates with one gate for each bistable circuit coupled between that bistable circuit and the output terminal which is associated with a bit of the same predetermined significance, and a first decoder adapted to receive virtual addresses and provide a number of unique output signals, one for and associated with each virtual address in dependence on the virtual address received, the decoder being connected to apply each output signal as an enabling signal to those gates in the first group which are coupled to bistable circuits associated with the same virtual address as that output signal.

Claim 9

Apparatus according to claim 7 wherein the logic means includes first and second groups of second bistable circuits each having the same number of bistable circuits as each first group of bistable circuits, each second bistable circuit in a group being associated with a respective bit significance in a virtual address, each bistable circuit in each group having a set terminal to which signals are applied to change the conduction state of that circuit and an output terminal the voltage of which indicates the conduction state currently present in the bistable circuit, second, third and fourth groups of gates, the first and second groups of gates being coupled between the output terminals of the first bistable circuits and the set terminals of the first and second groups, respectively, of the second bistable circuits to allow bistable circuit conduction states to be transferred from the first to second bistable circuits associated with the same virtual address bit significances, the third and fourth groups of gates being coupled between the output terminals of the first and second groups, respectively, of the second bistable circuits and the set terminal of the first bistable circuits to allow bistable circuit conduction states to be transferred from second to first bistable circuits associated with the same virtual address bit significances, second decoder means adapted to receive a virtual address and to provide a unique output signal associated with each virtual address, the first and second decoder means being connected to apply each of their output signals as an enabling signal to those gates, in the first and fourth groups, and second and third groups, respectively, which are coupled to first bistable circuits associated with the same virtual address as that output signal, and a pulse generator connected to apply first pulses as enabling signals to gates in the first and second groups and subsequently second pulses as enabling signals to gates in the third and fourth groups wherever a change in virtual address is to be made.

Claim 10

Apparatus according to claim 8, wherein there are two bistable circuits in each group, and each bistable circuit is associated with a more significant bit.