Semiconductor memory device capable of driving divided word lines at high speed

Claim 2

A semiconductor memory device, comprising: a plurality of memory cell regions each including a plurality of word lines; first selecting signal generating means responsive to a more significant bit of an externally applied address signal for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means responsive to a less significant bit of said externally applied address signal for generating a second selecting signal for selecting one word line in each memory cell region; a plurality of word line driving circuits each connected to a corresponding word line in one of said plurality of memory cell regions responsive to the first and second selecting signals for driving said corresponding one word line; each of said word line driving circuits including; transfer gate means having an output node responsive to one of the first and second selecting signals for transmitting the other one of the first and second selecting signals through said output node; driving means responsive to the potential at the output node of said transfer gate means for driving said corresponding one word line; resistor means connected between a first supply potential and the output node of said transfer gate means; and accelerating means connected between said first supply potential and the output node of said transfer gate means responsive to said one of the first and second selecting signals for accelerating charging or discharging of the output node of said transfer gate means.

Claim 3

The semiconductor memory device according to claim 1, wherein said first selecting signal generating means includes more significant address decoder means for decoding a more significant bit of said externally applied address signal to generate the first selecting signal for selecting one of said plurality of memory cell regions, and said second selecting signal generating means includes less significant address decode means for decoding a less significant bit of said externally applied address signal to generate the second selecting signal for selecting one word line in each memory cell region.

Claim 4

The semiconductor memory device according to claim 2, further comprising a plurality of main word lines connected to said plurality of memory cell regions, respectively, wherein said more significant address decoder means includes a global decoder for decoding a more significant bit of said externally applied address signal to selectively activate one of said plurality of main word lines.

Claim 5

The semiconductor memory device according to claim 1, wherein said driving means includes inverter means for inverting the potential signal at the output node of said transfer gate means to drive said corresponding one word line.

Claim 6

The semiconductor memory device according to claim 1, wherein said transfer gate means includes a first field effect transistor of a first conductivity type having an input electrode, an output electrode, and a gate electrode, and said first field effect transistor has the gate electrode connected to receive one of the first and second selecting signals, the input electrode connected to receive the other one of the first and second selecting signals, and the output electrode connected to the input of said driving means.

Claim 7

The semiconductor memory device according to claim 5, wherein said accelerating means includes a second field effect transistor of a second conductivity type connected between said supply potential and the output node of said transfer gate means and having a gate electrode connected to receive the one of the first and second selecting signals.

Claim 8

The semiconductor memory device according to claim 6, wherein said resistor means includes a third field effect transistor of the second conductivity type connected between said first supply potential and the output node of said transfer gate means and having a gate connected to a second supply potential.

Claim 9

The semiconductor memory device according to claim 7, wherein said inverter means includes a fourth field effect transistor of the second conductivity type and a fifth field effect transistor of the first conductivity type connected in series between said first and second supply potentials, and said fourth and fifth field effect transistors have their gates connected to the output node of said transfer gate means.

Claim 10

The semiconductor memory device according to claim 1, wherein said semiconductor memory device includes a static random access memory device (SRAM).

Claim 11

A word line driving circuit responsive to first and second selecting signals for driving a selected word line, comprising: transfer gate means having an output node responsive to the first selecting signal for transmitting the second selecting signal through said output node; driving means responsive to the potential at the output node of said transfer gate means for driving said word line; resistor means connected between a supply potential and the output node of said transfer gate means; and accelerating means connected between said supply potential and the output node of said transfer gate means responsive to the first selecting signal for accelerating charging or discharging of the output node of said transfer gate means.

Claim 12

A word line driving circuit responsive to first and second selecting signals for driving a selected word line, comprising: transfer gate means having an output node responsive to the first selecting signal for transmitting the second selecting signal through said output node; driving means responsive to the potential at the output node of said transfer gate means for driving said word line; resistor means connected between a supply potential and the output node of said transfer gate means; and accelerating means connected between said supply potential and the output node of said transfer gate means responsive to the first selecting signal for accelerating charging or discharging of the output node of said transfer gate means.

Claim 13

A semiconductor memory device, comprising: a plurality of memory cell regions each including a plurality of word lines; first selecting signal generating means responsive to a more significant bit of an externally applied address signal for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means responsive to a less significant bit of said externally applied address signal for generating a second selecting signal for selecting one word line in each memory cell region; and a plurality of word line driving circuits each connected to corresponding one word line in one of said plurality of memory cell regions responsive to the first and second selecting signals for driving said corresponding one word line; each of said word line driving circuits including; first and second input nodes for receiving one and the other of the first and second selecting signals, respectively, first and second switching elements connected in series between said first input node and a supply potential and turned on in a complementary manner in response to the second selecting signal applied through said second input node, said corresponding one word line being connected to a common connection node of said first and second switching elements, and a third switching element connected between said first input node and said corresponding one word line and turned on in response to the potential at the common connection node of said first and second switching elements.

Claim 14

A semiconductor memory device, comprising: a plurality of memory cell regions each including a plurality of word lines; first selecting signal generating means responsive to a more significant bit of an externally applied address signal for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means responsive to a less significant bit of said externally applied address signal for generating a second selecting signal for selecting one word line in each memory cell region; and a plurality of word line driving circuits each connected to corresponding one word line in one of said plurality of memory cell regions responsive to the first and second selecting signals for driving said corresponding one word line; each of said word line driving circuits including; first and second input nodes for receiving one and the other of the first and second selecting signals, respectively, first and second switching elements connected in series between said first input node and a supply potential and turned on in a complementary manner in response to the second selecting signal applied through said second input node, said corresponding one word line being connected to a common connection node of said first and second switching elements, and a third switching element connected between said first input node and said corresponding one word line and turned on in response to the potential at the common connection node of said first and second switching elements.

Claim 15

The semiconductor memory device according to claim 11, wherein said first switching element includes a first field effect transistor of a first conductivity type, said second switching element includes a second field effect transistor of a second conductivity type opposite to the first conductivity type, and said first and second field effect transistors are connected in series between said first input node and supply potential and have the gates connected to said second input node.

Claim 16

The semiconductor memory device according to claim 11, wherein said semiconductor memory device includes a static random access memory device (SRAM).

Claim 17

A semiconductor memory device, comprising: a plurality of memory cell regions each including a plurality of word lines; first selecting signal generating means responsive to a more significant bit of an externally applied address signal for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means responsive to a less significant bit of said externally applied address signal for generating a second selecting signal for selecting one word line in each memory cell region; and a plurality of word line driving circuits each connected to corresponding one word line in one of said plurality of memory cell regions responsive to the first and second selecting signals for driving said corresponding one word line; each of said word line driving circuits including: first and second switching elements connected in series between said first input node and a supply potential and turned on in a complementary manner in response to the second selecting signal applied through said second input node, said corresponding one word line being connected to a common connection node of said first and second switching elements, and a third switching element connected between said first input node and said corresponding one word line and turned on in response to the potential at the common connection node of said first and second switching elements, wherein said first switching element includes a first field effect transistor of a first conductivity type, said second switching element includes a second field effect transistor of a second conductivity type opposite to the first conductivity type. said first and second field effect transistors are connected in series between said first input node and supply potential and have the gates connected to said second input node, and said third switching element includes a third field effect transistor of the second conductivity type connected between said first input node and said corresponding one word line and having the gate connected to the common connection node of said first and second field effect transistors.

Claim 18

A semiconductor memory device, comprising: a plurality of memory cell regions each including a plurality of word lines; first selecting signal generating means responsive to a more significant bit of an externally applied address signal for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means responsive to a less significant bit of said externally applied address signal for generating a second selecting signal for selecting one word line in each memory cell region; and a plurality of word line driving circuits each connected to corresponding one word line in one of said plurality of memory cell regions responsive to the first and second selecting signals for driving said corresponding one word line; each of said word line driving circuits including: first and second switching elements connected in series between said first input node and a supply potential and turned on in a complementary manner in response to the second selecting signal applied through said second input node, said corresponding one word line being connected to a common connection node of said first and second switching elements, and a third switching element connected between said first input node and said corresponding one word line and turned on in response to the potential at the common connection node of said first and second switching elements, wherein said first switching element includes a first field effect transistor of a first conductivity type, said second switching element includes a second field effect transistor of a second conductivity type opposite to the first conductivity type. said first and second field effect transistors are connected in series between said first input node and supply potential and have the gates connected to said second input node, and said third switching element includes a third field effect transistor of the second conductivity type connected between said first input node and said corresponding one word line and having the gate connected to the common connection node of said first and second field effect transistors.

Claim 19

The semiconductor memory device according to claim 14, further comprising resistor means connected between the common connection node of said first and second field effect transistors and said supply potential, wherein said third field effect transistor has a lower threshold voltage as compared to that of said second field effect transistor.

Claim 20

A word line driving circuit responsive to first and second selecting signals for driving a selected word line, comprising: first and second input nodes for receiving the first and second selecting signals, respectively; first and second switching elements connected in series between said first input node and a supply potential and turned on in a complementary manner in response to the second selecting signal applied through said second input node; said word line being connected to a common connection node of said first and second switching elements; and a third switching element connected between said first input node and said word line and turned on in response to the potential at the common connection node of said first and second switching elements.

Claim 21

A word line driving circuit responsive to first and second selecting signals for driving a selected word line, comprising: first and second input nodes for receiving the first and second selecting signals, respectively; first and second switching elements connected in series between said first input node and a supply potential and turned on in a complementary manner in response to the second selecting signal applied through said second input node; said word line being connected to a common connection node of said first and second switching elements; and a third switching element connected between said first input node and said word line and turned on in response to the potential at the common connection node of said first and second switching elements.

Claim 22

A semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of memory cells; each of said memory cell arrays including a plurality of memory cell regions each including one or a plurality of word lines; first selecting signal generating means for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means for generating a second selecting signal for selecting one of said plurality of memory cell array blocks; a plurality of word line driving circuits for driving the one or plurality of word lines in said memory cell regions in response to the first selecting signal and the second selecting signal; each of said word line driving circuits including; transfer gate means having an output node responsive to one of the first and second selecting signals for transmitting the other one of the first and second selecting signals through said output node; driving means responsive to the potential at the output node of said transfer gate means for driving said corresponding one word line; resistor means connected between a first supply potential and the output node of said transfer gate means; and accelerating means connected between said first supply potential and the output node of said transfer gate means responsive to said one of the first and second selecting signals for accelerating charging or discharging of the output node of said transfer gate means.

Claim 23

A semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of memory cells; each of said memory cell arrays including a plurality of memory cell regions each including one or a plurality of word lines; first selecting signal generating means for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means for generating a second selecting signal for selecting one of said plurality of memory cell array blocks; a plurality of word line driving circuits for driving the one or plurality of word lines in said memory cell regions in response to the first selecting signal and the second selecting signal; each of said word line driving circuits including; transfer gate means having an output node responsive to one of the first and second selecting signals for transmitting the other one of the first and second selecting signals through said output node; driving means responsive to the potential at the output node of said transfer gate means for driving said corresponding one word line; resistor means connected between a first supply potential and the output node of said transfer gate means; and accelerating means connected between said first supply potential and the output node of said transfer gate means responsive to said one of the first and second selecting signals for accelerating charging or discharging of the output node of said transfer gate means.

Claim 24

A semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of memory cells; each of said memory cell arrays including a plurality of memory cell regions each including one or a plurality of word lines; first selecting signal generating means for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means for generating a second selecting signal for selecting one of said plurality of memory cell array blocks; a plurality of word line driving circuits for driving the one or plurality of word lines in said memory cell regions in response to the first selecting signal and the second selecting signal; each of said word line driving circuits including; first and second input nodes for receiving one and the other of the first and second selecting signals, respectively, first and second switching elements connected in series between said first input node and a supply potential and turned on in a complementary manner in response to the second selecting signal applied through said second input node, said corresponding one word line being connected to a common connection node of said first and second switching elements, and a third switching element connected between said first input node and said corresponding one word line and turned on in response to the potential at the common connection node of said first and second switching elements.

Claim 25

A semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of memory cells; each of said memory cell arrays including a plurality of memory cell regions each including one or a plurality of word lines; first selecting signal generating means for generating a first selecting signal for selecting one of said plurality of memory cell regions; second selecting signal generating means for generating a second selecting signal for selecting one of said plurality of memory cell array blocks; a plurality of word line driving circuits for driving the one or plurality of word lines in said memory cell regions in response to the first selecting signal and the second selecting signal; each of said word line driving circuits including; first and second input nodes for receiving one and the other of the first and second selecting signals, respectively, first and second switching elements connected in series between said first input node and a supply potential and turned on in a complementary manner in response to the second selecting signal applied through said second input node, said corresponding one word line being connected to a common connection node of said first and second switching elements, and a third switching element connected between said first input node and said corresponding one word line and turned on in response to the potential at the common connection node of said first and second switching elements.