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US5272452A Expired / Lapsed US ⏱️ 0.0 years remaining

PLL frequency synthesizer with variable bandwidth loop filter

Assignee: Panasonic Holdings Corp
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Filing: 1992-08-20
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Granted: 1993-12-21
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Expires: 2012-08-20
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Abstract

Abstract A voltage controlled oscillator (VCO), a frequency divider, a phase detector, and a loop filter are connected to form a phase-locked loop. The input line of the loop filter is branched into two. One branch is connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series. The other branch is connected between the second resistor and the capacitor through a switch and a bypass resistor which are connected in series. The connection point of the first resistor and second resistor are connected to the VCO as the output terminal of the loop filter. When the switch is off, the bandwidth of the loop filter is narrow, and when the switch is on, the bandwidth of the loop filter is broad.

Inventors

  • 👤 Hisashi Adachi
  • 👤 Hiroaki Kosugi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 21:50
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/08; H03L7/10; H03L7/107; H03L7/1075

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 165 words
A PLL frequency synthesizer comprising: a voltage controlled oscillator, a frequency divider for dividing a frequency of an output of the voltage controlled oscillator; a phase detector for comparing a phase of an output of the frequency divider with a phase of a reference signal to obtain a phase difference signal; and a loop filter for smoothing the phase difference signal from the phase detector and delivering the smoothed signal to the voltage controlled oscillator, wherein the loop filter has an input terminal branched into two, one branch being connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series, the other branch being connected between the second resistor and the capacitor through a switch and a bypass resistor which are connected in series, a connection point of the first resistor and the second resistor being connected to the voltage controlled oscillator, and the switch being turned on or off by an externally given switch control signal.
Claim 2
Dependent Claim 165 words
A PLL frequency synthesizer comprising: a voltage controlled oscillator, a frequency divider for dividing a frequency of an output of the voltage controlled oscillator; a phase detector for comparing a phase of an output of the frequency divider with a phase of a reference signal to obtain a phase difference signal; and a loop filter for smoothing the phase difference signal from the phase detector and delivering the smoothed signal to the voltage controlled oscillator, wherein the loop filter has an input terminal branched into two, one branch being connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series, the other branch being connected between the second resistor and the capacitor through a switch and a bypass resistor which are connected in series, a connection point of the first resistor and the second resistor being connected to the voltage controlled oscillator, and the switch being turned on or off by an externally given switch control signal.
Claim 3
Dependent Claim 46 words
A PLL frequency synthesizer of claim 1, further comprising a buffer amplifier provided between the input terminal of the loop filter and the first resistor, whrein the switch is a 3-state buffer amplifier, whose output is set in high impedance state by the switch control signal.
Claim 4
Dependent Claim 34 words
A PLL frequency synthesizer of claim 1, further comprising a low pass filter provided between the connection point of the first resistor and the second resistor and the output terminal of the loop filter.
Claim 5
Dependent Claim 37 words
A PLL frequency synthesizer of claim 3, wherein the low pass filter comprises a plurality of stages of filters each comprising a resistor connected in series and a capacitor to be branched and connected to the ground.
Claim 6
Dependent Claim 48 words
A PLL frequency synthesizer of claim 1, wherein the first resistor is divided into two by a dividing point, and the dividing point and the input terminal of the loop filter are connected through a second switch which is turned on or off by the switch control signal.
Claim 7
Dependent Claim 174 words
A PLL frequency synthesizer comprising: a voltage controlled oscillator; a frequency divider for dividing a frequency of an output of the voltage controlled oscillator; a phase detector for comparing a phase of an output of the frequency divider with a phase of a reference signal to obtain a phase difference signal; and a loop filter for smoothing the phase difference signal from the phase detector and delivering the smoothed signal to the voltage controlled oscillator, wherein the loop filter has an input terminal branched into two, one branch being connected to a low pass filter whose output is connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series, the other branch being connected between the second resistor and the capacitor through a switch and a bypass resistor which are connected in series, a connection point of the first resistor and the second resistor being connected to the voltage controlled oscillator, and the switch being turned on or off by an externally given switch control signal.
Claim 8
Dependent Claim 174 words
A PLL frequency synthesizer comprising: a voltage controlled oscillator; a frequency divider for dividing a frequency of an output of the voltage controlled oscillator; a phase detector for comparing a phase of an output of the frequency divider with a phase of a reference signal to obtain a phase difference signal; and a loop filter for smoothing the phase difference signal from the phase detector and delivering the smoothed signal to the voltage controlled oscillator, wherein the loop filter has an input terminal branched into two, one branch being connected to a low pass filter whose output is connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series, the other branch being connected between the second resistor and the capacitor through a switch and a bypass resistor which are connected in series, a connection point of the first resistor and the second resistor being connected to the voltage controlled oscillator, and the switch being turned on or off by an externally given switch control signal.
Claim 9
Dependent Claim 37 words
A PLL frequency synthesizer of claim 6, wherein the low pass filter comprises a plurality of stages of filters each comprising a resistor connected in series and a capacitor to be branched and connected to the ground.
Claim 10
Dependent Claim 47 words
A PLL frequency synthesizer of claim 7, further comprising a buffer amplifier provided between the input terminal of the loop filter and the low pass filter, wherein the switch is a 3-state buffer amplifier whose output is set in high impedance state by the switch control signal.
Claim 11
Dependent Claim 198 words
A PLL frequency synthesizer comprising: a voltage controlled oscillator, a frequency divider for dividing a frequency of an output of the voltage controlled oscillator; a phase detector for comparing a phase of an output of the frequency divider with a phase of a reference signal to obtain a phase difference signal; and a loop filter for smoothing the phase difference signal from the phase detector and delivering the smoothed signal to the voltage controlled oscillator, wherein the loop filter has an input terminal branched into three, one branch being connected to a low pass filter whose output is connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series, a second branch being connected between the second resistor and the capacitor through a first switch and a bypass resistor which are connected in series, a final branch being connected between the low pass filter and the first resistor through a second switch, a connection point of the first resistor and the second resistor being connected to the voltage controlled oscillator, and the first switch and the second switch are turned on or off by an externally given switch control signal.
Claim 12
Dependent Claim 198 words
A PLL frequency synthesizer comprising: a voltage controlled oscillator, a frequency divider for dividing a frequency of an output of the voltage controlled oscillator; a phase detector for comparing a phase of an output of the frequency divider with a phase of a reference signal to obtain a phase difference signal; and a loop filter for smoothing the phase difference signal from the phase detector and delivering the smoothed signal to the voltage controlled oscillator, wherein the loop filter has an input terminal branched into three, one branch being connected to a low pass filter whose output is connected to the ground through a first resistor, a second resistor and a capacitor which are connected in series, a second branch being connected between the second resistor and the capacitor through a first switch and a bypass resistor which are connected in series, a final branch being connected between the low pass filter and the first resistor through a second switch, a connection point of the first resistor and the second resistor being connected to the voltage controlled oscillator, and the first switch and the second switch are turned on or off by an externally given switch control signal.
Claim 13
Dependent Claim 37 words
A PLL frequency synthesizer of claim 9, wherein the low pass filter comprises a plurality of stages of filters each comprising a resistor connected in series and a capacitor to be branched and connected to the ground.
Claim 14
Dependent Claim 47 words
A PLL frequency synthesizer of claim 10, further comprising a buffer amplifier provided between the input terminal of the loop filter and the low pass filter, wherein each switch is a 3-state buffer amplifier whose output is set in high impedance state by the switch control signal.
Claim 15
Dependent Claim 48 words
A PLL frequency synthesizer of claim 3 wherein the first resistor is divided into two by a dividing point, and the dividing point and the input terminal of the loop filter are connected through a second switch which is turned on or off by the switch control signal.
Claim 16
Dependent Claim 48 words
A PLL frequency synthesizer of claim 4 wherein the first resistor is divided into two by a dividing point, and the dividing point and the input terminal of the loop filter are connected through a second switch which is turned on or off by the switch control signal.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-12-20 1997-06-21 1997-12-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-12-20 2001-06-21 2001-12-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-12-20 2005-06-21 2005-12-21 $7700.00 Window Closed / Lapsed

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