Data transfer method performed in a data processor provided in a switching system

Claim 1

A data processor used in a switching system, for processing a packet data transferred in the data processor, said data processor comprising: central control equipment for controlling a transfer process of the packet data, said central control equipment comprising: means for adding a header to the packet data, the header specifying a data length of the packet data, means for dividing the header and the packet data to a plurality of data blocks comprising an initial data block including the header and an initial part of the packet data, a plurality of intermediate data blocks each including an intermediate part of the packet data and a last data block including a last part of the packet data, so that each of the data blocks has a designated data length, and means for producing write commands, the write commands comprising a first write command, a plurality of second write commands and a third write command, the first write command indicating that a data block commanded by the first write command is the initial data block and specifying a transfer direction and address of the initial data block, the second write command indicating that a data block commanded by the second write command is the intermediate data block and specifying a transfer direction and address of each of the intermediate data blocks and the third write command indicating that a data block commanded by the third write command is the last data block and specifying a transfer direction and address of the last data block; a main memory comprising: first memory means for storing the data blocks, and second memory means for storing the write commands; and line control equipment comprising: control means for controlling transfer of the data blocks stored in said first memory means, for controlling the storing of the data blocks transferred from said first memory means and for controlling the transfer and the storing in accordance with the write commands stored in said second memory means, third memory means for storing the data blocks transferred from said first memory means, and processor means for restoring the packet data by synthesizing the data blocks stored in said third memory means and for removing the header from the data blocks stored in said third memory means.