Integrated communications system for HDLC variable-length data packets and fixed-length voice/video packets

Claim 3

A method as claimed in claim 1, wherein said cell identifier is a block code comprising cell identification bits and error correcting bits, wherein the step (f) comprises correcting error contained in said cell identification bits of each cell identifier using the error correcting bits of the cell identifier.

Claim 4

An integrated communications system comprising: an HDLC (high level data link control) variable-length packet transmitter; a non-HDLC fixed-length packet transmitter; a transmit shift register having an input terminal connected to said packet transmitters and an output terminal connected to one end of a transmission medium; a sync generator for supplying a sync code to said transmit shift register at periodic intervals; a header generator; cell formatting means for activating for a predetermined period one of said packet transmitters having a packet of one of variable length and fixed length to transmit so that a portion of said packet is supplied to said transmit shift register as a cell, causing said header generator to supply a cell identifier identifying a type of the packet from which said cell is decomposed to said transmit shift register to form a field with said cell, and causing said transmit shift register to assemble said sync code and a plurality of said fields into a frame and transmitting the frame through said transmission medium; a receive shift register having an input terminal connected to the other end of said transmission medium, said receive shift register being supplied with said transmitted frame; a sync detector for detecting the sync code contained in the frame supplied to said receive shift register; a header detector responsive to the detection of a sync code by said sync detector for detecting the cell identifier of each field of the frame in said receive shift register; a HDLC variable-length packet receiver; a non-HDLC fixed-length packet receiver; and cell deformatting means responsive to the cell identifier detected by said header detector for activating for said predetermined period one of said packet receivers so that said portion of said packet is supplied from said receive shift register to said one of the packet receivers.

Claim 5

An integrated communications system comprising: an HDLC (high level data link control) variable-length packet transmitter; a non-HDLC fixed-length packet transmitter; a transmit shift register having an input terminal connected to said packet transmitters and an output terminal connected to one end of a transmission medium; a sync generator for supplying a sync code to said transmit shift register at periodic intervals; a header generator; cell formatting means for activating for a predetermined period one of said packet transmitters having a packet of one of variable length and fixed length to transmit so that a portion of said packet is supplied to said transmit shift register as a cell, causing said header generator to supply a cell identifier identifying a type of the packet from which said cell is decomposed to said transmit shift register to form a field with said cell, and causing said transmit shift register to assemble said sync code and a plurality of said fields into a frame and transmitting the frame through said transmission medium; a receive shift register having an input terminal connected to the other end of said transmission medium, said receive shift register being supplied with said transmitted frame; a sync detector for detecting the sync code contained in the frame supplied to said receive shift register; a header detector responsive to the detection of a sync code by said sync detector for detecting the cell identifier of each field of the frame in said receive shift register; a HDLC variable-length packet receiver; a non-HDLC fixed-length packet receiver; and cell deformatting means responsive to the cell identifier detected by said header detector for activating for said predetermined period one of said packet receivers so that said portion of said packet is supplied from said receive shift register to said one of the packet receivers.

Claim 6

An integrated communications system as claimed in claim 3, wherein said cell formatting means assembles cells from said HDLC variable-length packet transmitter with cells from said non-HDLC fixed-length packet transmitter in a common frame.

Claim 7

An integrated communications system as claimed in claim 3, wherein said cell identifier is encoded with error correcting bits, wherein said header detector corrects an error contained in said cell identifier using said error correcting bits.

Claim 8

An integrated communications system as claimed in claim 3, wherein said header detector comprises a memory for storing 2 n bits, where n indicates a total number of bits contained in said cell identifier and reading one of said stored 2 n bits in response to said cell identifier.

Claim 9

An integrated communications system as claimed in claim 3, further comprising a flag generator for generating a predetermined bit pattern, wherein said cell formatting means causes said flag generator to supply said bit pattern to said transmit shift register as a cell in the absence of a packet to transmit in any of said packet transmitters.

Claim 10

An integrated communications system as claimed in claim 3, wherein said non-HDLC fixed-length packet transmitter comprises: a short-length packet transmitter for transmitting a short packet having a length equal to the length of said cell; and a long-length packet transmitter for transmitting a long packet having a length equal to an integral multiple of the length of said cell, wherein said cell identifier identifies different cells of said long packet with respective cell identifiers, wherein said fixed-length packet receiver comprises: a short-length packet receiver for assembling the cells identified by said cell identifier into said short packet; and a long-length packet receiver for assembling the cells identified by said respective cell identifiers into said long packet.

Claim 11

An integrated communications system as claimed in claim 8, wherein said long packet comprises an integral multiple of the number of bits contained in said short packet.

Claim 12

An integrated communications system as claimed in claim 3, further comprising means for selecting one of said packet transmitters according to a predetermined priority algorithm and causing said cell formatting means to activate said selected one of said packet transmitters.

Claim 13

An integrated communications system as claimed in claim 3, wherein said cell formatting means continuously drives said transmit shift registers with clock pulses and drives said one of said packet transmitters with said clock pulses for said predetermined duration to transfer bits from the driven packet transmitter to said shift register.