Variable length packet switching system

Claim 2

In a packet switching system having a plurality of ports interconnected by a communication cable comprising a data bus and arbitration conductor and arbitration frame conductor and data frame conductor and control bus and a packet switch controller for initializing said ports via said control bus and each of said ports interconnected to a terminal controller that serves a plurality of customer terminals, each of said ports comprising: an address storage memory having been initialized by said packet switch controller via said control bus responsive to receipt of data from one of the customer terminals via the interconnected terminal controller to be transmitted over said data bus to another port for accessing stored address information identifying said other port; a temporary memory for storing remaining data from said customer terminal; a first-in first-out memory responsive to the accessed address information and the remaining data for forming a packet; a first detector circuit responsive to the end of said data having been stored in said first-in first-out memory for generating a signal indicating said end of said data; an arbitration circuit reponsive to said signal indicating said end of said data for requesting access to said data bus on behalf of said port by signaling on said arbitration conductor; said arbitration circuit further responsive to a signal on said arbitration frame conductor indicating access granted to said data bus for generating a signal indicating said port selected to access said data bus; a gate circuit for determining the concurrence of said signal indicating said port selection and a signal received via said data framing conductor indicating that said data bus is idle; a control circuit responsive to the concurrence determination for applying a busy signal to said data frame conductor; a clock enable circuit responsive to said concurrence determination for transmitting clock signals to said first-in first-out memory; said first-in first-out memory responsive to said clock signals for transmitting the formed packet on said data bus; said clock enable circuit further responsive to the application of said busy signal by said control circuit to said data frame conductor for continuously applying said busy signal to said data frame conductor; a second detector circuit for determining the end of transmission of said packet on said data bus; and said clock enable circuit further responsive to the determination of said end of transmission of said packet for ceasing to apply said busy signal to said data frame conductor.

Claim 3

The system of claim 1 wherein said control circuit comprises: a first flip-flop responsive to the concurrence determination for switching from a first to a second state; an OR circuit responsive to said first flip-flop being in said second state for generating said busy signal; and a bus driver circuit responsive to the generated busy signal for transmitting said generated busy signal on said data frame conductor.

Claim 4

The system of claim 2 wherein said second detector further responsive to a portion of said packet remaining in said first-in first-out memory for generating a signal indicating that the transmission of said packet is still continuing; said clock enable circuit comprises a first AND gate responsive to the signal indicating the continuation of transmission of said packet and the transmission of said busy signal for generating a flip-flop control signal; a second flip-flop responsive to said flip-flop control signal for switching from a first to a second state to control the application of said busy signal to said data frame conductor via said OR gate; and a second AND gate responsive to said transmission of said busy signal and clock signals for retransmitting said clock signals to said first-in first-out memory.

Claim 5

The system of claim 2 wherein said OR gate circuit responsive to said second flip-flop being in said second state for continuously applying said busy signal to said data frame conductor via said bus driver circuit.

Claim 6

The system of claim 4 wherein said first detector circuit comprises a subcircuit for determining the end of data from said terminal controller; and a third flip-flop responsive to the determination of the end of data from said terminal controller for switching from a first to a second state thereby generating said signal indicating said end of said data.

Claim 7

In a packet switching system having a plurality of ports interconnected by a communication cable comprising a data bus and arbitration conductor and arbitration frame conductor and data frame conductor and control bus and a packet switch controller for initializing said ports via said control bus and each of said ports interconnected to a terminal controller that serves a plurality of customer terminals, each of said ports comprising: an address storage memory for storing address memory identifying ports on said system; said packet switch controller responsive to an initialization of said system for writing said address information into said address storage memory; said address storage memory responsive to receipt of data from one of the customer terminals via the interconnected terminal controller to be transmitted over said data bus to another port for accessing said stored address information identifying said other port; each of said ports further comprising a temporary memory for storing remaining data from said customer terminal; a first-in first-out memory responsive to the accessed address information and the remaining data for forming a packet; a first detector circuit for determining the end of data from said terminal controller; a first flip-flop responsive to the determination of the end of data from said terminal controller for switching from a first to a second state thereby generating a signal indicating the end of said data; an arbitration circuit responsive to said signal indicating said end of said data for requesting access to said data bus on behalf of said port by signaling via said arbitration conductor; said arbitration circuit further responsive to a signal received via said arbitration frame conductor indicating access granted to said data bus for generating a signal indicating said port selected to access said data bus; a gate circuit for determining the concurrence of said signal indicating said port selected and a signal received via said data framing conductor indicating that said data bus is idle; a second flip-flop responsive to the concurrence determination for switching from a first to a second state; an OR circuit responsive to said second flip-flop being in said second state for generating a busy signal; a bus driver circuit responsive to the generated busy signal for transmitting said generated busy signal on said data frame conductor; a second detector circuit responsive to a portion of said packet remaining in said first-in first-out memory for generating a signal indicating that the transmission of said packet is still continuing; a first AND gate responsive to the signal indicating the continuation of transmission of said packet and the transmission of said busy signal for generating a flip-flop control signal; a third flip-flop responsive to said flip-flop control signal for switching from a first to a second state; said OR gate further responsive to said third flip-flop being in said second state for continuously applying said busy signal to said data frame conductor; a second AND gate responsive to said transmission of said busy signal by said OR gate and clock signals for retransmitting said clock signals to said first-in first-out memory; and said first-in first-out memory responsive to said clock signals for transmitting the formed packet to said data bus.

Claim 8

In a packet switching system having a plurality of ports interconnected by a communication cable comprising a data bus and arbitration conductor and arbitration frame conductor and data frame conductor and control bus and a packet switch controller for initializing said ports via said control bus and each of said ports interconnected to a terminal controller that serves a plurality of customer terminals, each of said ports comprising: an address storage memory for storing address memory identifying ports on said system; said packet switch controller responsive to an initialization of said system for writing said address information into said address storage memory; said address storage memory responsive to receipt of data from one of the customer terminals via the interconnected terminal controller to be transmitted over said data bus to another port for accessing said stored address information identifying said other port; each of said ports further comprising a temporary memory for storing remaining data from said customer terminal; a first-in first-out memory responsive to the accessed address information and the remaining data for forming a packet; a first detector circuit for determining the end of data from said terminal controller; a first flip-flop responsive to the determination of the end of data from said terminal controller for switching from a first to a second state thereby generating a signal indicating the end of said data; an arbitration circuit responsive to said signal indicating said end of said data for requesting access to said data bus on behalf of said port by signaling via said arbitration conductor; said arbitration circuit further responsive to a signal received via said arbitration frame conductor indicating access granted to said data bus for generating a signal indicating said port selected to access said data bus; a gate circuit for determining the concurrence of said signal indicating said port selected and a signal received via said data framing conductor indicating that said data bus is idle; a second flip-flop responsive to the concurrence determination for switching from a first to a second state; an OR circuit responsive to said second flip-flop being in said second state for generating a busy signal; a bus driver circuit responsive to the generated busy signal for transmitting said generated busy signal on said data frame conductor; a second detector circuit responsive to a portion of said packet remaining in said first-in first-out memory for generating a signal indicating that the transmission of said packet is still continuing; a first AND gate responsive to the signal indicating the continuation of transmission of said packet and the transmission of said busy signal for generating a flip-flop control signal; a third flip-flop responsive to said flip-flop control signal for switching from a first to a second state; said OR gate further responsive to said third flip-flop being in said second state for continuously applying said busy signal to said data frame conductor; a second AND gate responsive to said transmission of said busy signal by said OR gate and clock signals for retransmitting said clock signals to said first-in first-out memory; and said first-in first-out memory responsive to said clock signals for transmitting the formed packet to said data bus.

Claim 9

The system of claim 6 wherein said second detector circuit further responsive to the end of transmission of said packet for generating a signal indicating said end of transmission of said packet on said data bus; said first AND circuit further responsive to said signal indicating said end of said packet for generating another flip-flop control signal; and said third flip-flop being further responsive to said other flip-flop control signal for switching from said second state to said first state.