Patent US5268310A successfully refreshed from Google Patents.
US5268310A
Expired / Lapsed
US
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Method for making a mesa type PIN diode
Assignee: MACOM Technology Solutions Holdings Inc
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Filing: 1992-11-25
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Granted: 1993-12-07
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Expires: 2012-11-25
Abstract
Abstract A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.
Inventors
- 👤 Joel L. Goodrich
- 👤 Christopher C. Souchuns
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:58
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/01; H10D8/021; H10D8/024; H10D84/00; H10D84/201; H10D84/204; H10W; H10W72/00; H10W72/30; H10W74/00; H10W74/01; H10W70/00; H10W70/099; H10W70/60; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336; H10W72/851; H10W72/874
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
151 words
A method for fabricating a PIN diode, and comprising the steps of: a. forming an insulating layer on an intrinsic layer disposed upon an N-type substrate; b. forming in said insulating layer an opening to a first region of said intrinsic layer; c. forming in said first region a P-type junction of predetermined area; d forming upon said insulating layer and said junction a dielectric layer; e. forming a dielectric pad region by removing both said dielectric layer and said insulating layer except in a second region located on and surrounding said junction, said second region having an area which is greater than said predetermined area of said junction; f. removing said dielectric layer from said second region; g. forming a mesa having side-walls and a top surface in said intrinsic layer beneath said pad region; and h. forming an N-type, highly doped conducting layer in said side-walls of said mesa.
Claim 2
Independent Claim
151 words
A method for fabricating a PIN diode, and comprising the steps of: a. forming an insulating layer on an intrinsic layer disposed upon an N-type substrate; b. forming in said insulating layer an opening to a first region of said intrinsic layer; c. forming in said first region a P-type junction of predetermined area; d forming upon said insulating layer and said junction a dielectric layer; e. forming a dielectric pad region by removing both said dielectric layer and said insulating layer except in a second region located on and surrounding said junction, said second region having an area which is greater than said predetermined area of said junction; f. removing said dielectric layer from said second region; g. forming a mesa having side-walls and a top surface in said intrinsic layer beneath said pad region; and h. forming an N-type, highly doped conducting layer in said side-walls of said mesa.
Claim 3
Dependent Claim
19 words
A method according to claim 1, wherein the area of said second region is approximately twice said predetermined area.
Claim 4
Dependent Claim
14 words
A method according to claim 1, wherein said conducting layer is doped with phosphorous.
Claim 5
Dependent Claim
21 words
A method according to claim 1, wherein the formation of said insulating layer at step a is accomplished by thermal oxidation.
Claim 6
Dependent Claim
18 words
A method according to claim 1, wherein the formation of said opening is accomplished by using photoresistive etching.
Claim 7
Dependent Claim
22 words
A method according to claim 1, wherein the formation of said junction is accomplished by implanting boron ions in said first region.
Claim 8
Dependent Claim
18 words
A method according to claim 1, wherein said dielectric layer is made of Si 3 N 4 .
Claim 9
Dependent Claim
40 words
A method according to claim 1, and further comprising extending said conducting layer onto the top surface of said mesa not occupied by said junction to form an electrical contact from said substrate to the top surface of said diode.
Claim 10
Dependent Claim
16 words
A method according to claim 1, and further comprising annealing said diode with a forming gas.
Claim 11
Dependent Claim
15 words
A method according to claim 1, and further comprising, encapsulating said diode in insulative material.
Claim 12
Independent Claim
128 words
A method for encapsulating a semiconductor device in an insulative material, said device having at least one component defining an irregularly shaped surface having at least one cavity, said method comprising the following steps: a. placing a quantity of said insulative material sufficient to encapsulate said device in intimate contact with said surface, said quantity being positioned on said surface so as to at least span said at least one component; b. subjecting said insulative material and said device to ambient conditions sufficient to cause said insulative material's viscosity to decrease such that said insulative material flows into said cavities; c. modifying said ambient conditions so as to prevent formation of void pockets between said insulative material and said surface; and d. permitting said insulative material to harden.
Claim 13
Independent Claim
128 words
A method for encapsulating a semiconductor device in an insulative material, said device having at least one component defining an irregularly shaped surface having at least one cavity, said method comprising the following steps: a. placing a quantity of said insulative material sufficient to encapsulate said device in intimate contact with said surface, said quantity being positioned on said surface so as to at least span said at least one component; b. subjecting said insulative material and said device to ambient conditions sufficient to cause said insulative material's viscosity to decrease such that said insulative material flows into said cavities; c. modifying said ambient conditions so as to prevent formation of void pockets between said insulative material and said surface; and d. permitting said insulative material to harden.
Claim 14
Dependent Claim
21 words
A method according to claim 11, wherein said at least one component comprises a diode fabricating method according to claim 1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |