US4373255A
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US
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Method of making oxide passivated mesa epitaxial diodes with integral plated heat sink
Assignee: United States Department of the Air Force
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Filing: 1981-06-03
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Granted: 1983-02-15
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Expires: 2001-06-03
Abstract
Abstract An oxide passivated mesa epitaxial diode with an integral heat sink, and a process by which it may be fabricated. The passivation layer of highly pure thermally grown SiO 2 is formed over the mesa walls in the region of the pn junction without causing a reaction between the contact metals and their surroundings during the high temperature environment imposed during thermal growth. The heat sink is deposited after the SiO 2 passivation has been grown, replacing a polycrystalline silicon layer beneath the mesa formation which was used as a temporary structural support. Dopant, to form the pn junction, is introduced into the silicon wafer after the formation of the passivation layer but before the heat sink is deposited.
Inventors
- 👤 Herbert Goronkin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:17
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/64; H10D8/00; H10D8/50; H10W; H10W40/00; H10W40/10; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/6875; Y; Y10; Y10S; Y10S438/00; Y10S438/928; Y10S438/977
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
305 words
A method of making a silicon mesa epitaxial diode, comprising the steps of: a. forming a silicon substrate having a heavily doped layer and a lightly doped layer, both layers being of the first conductivity type; b. thermally growing a thin layer of SiO 2 on the lightly doped layer; c. depositing a thick layer of polycrystalline silicon over the SiO 2 layer to serve as a temporary structural support; d. thermally growing a thin layer of SiO 2 on the heavily doped layer; e. depositing a thin layer of Si 3 N 4 over the SiO 2 grown in step d; defining a diode pattern on the Si 3 N 4 layer; g. etching through the Si 3 N 4 and the SiO 2 layers in the region outside the diode pattern; h. etching through the lightly and heavily doped layers of silicon to form a mesa-like structure; i. thermally growing a moderate thickness layer of SiO 2 on the sidewalls of said mesa-like structure and on the polycrystalline silicon; j. depositing a thick layer of polycrystalline silicon over the SiO 2 grown in step i; k. etching away the polycrystalline silicon temporary support structured deposited in step c; l. etching the SiO 2 exposed during step k from the surface of the lightly doped layer; m. introducing dopant of the second conductivity type, opposite that of the first, into the lightly doped layer; n. plating a thick layer of electrically and thermally conductive material on the area doped in step m; o. etching away the polycrystalline silicon deposited during step j; p. etching away the Si 3 N 4 over the diode pattern; q. etching the SiO 2 from the surface of the heavily doped layer; and r. depositing a layer of electrically conductive material on the surface of the heavily doped layer.
Claim 2
Independent Claim
305 words
A method of making a silicon mesa epitaxial diode, comprising the steps of: a. forming a silicon substrate having a heavily doped layer and a lightly doped layer, both layers being of the first conductivity type; b. thermally growing a thin layer of SiO 2 on the lightly doped layer; c. depositing a thick layer of polycrystalline silicon over the SiO 2 layer to serve as a temporary structural support; d. thermally growing a thin layer of SiO 2 on the heavily doped layer; e. depositing a thin layer of Si 3 N 4 over the SiO 2 grown in step d; defining a diode pattern on the Si 3 N 4 layer; g. etching through the Si 3 N 4 and the SiO 2 layers in the region outside the diode pattern; h. etching through the lightly and heavily doped layers of silicon to form a mesa-like structure; i. thermally growing a moderate thickness layer of SiO 2 on the sidewalls of said mesa-like structure and on the polycrystalline silicon; j. depositing a thick layer of polycrystalline silicon over the SiO 2 grown in step i; k. etching away the polycrystalline silicon temporary support structured deposited in step c; l. etching the SiO 2 exposed during step k from the surface of the lightly doped layer; m. introducing dopant of the second conductivity type, opposite that of the first, into the lightly doped layer; n. plating a thick layer of electrically and thermally conductive material on the area doped in step m; o. etching away the polycrystalline silicon deposited during step j; p. etching away the Si 3 N 4 over the diode pattern; q. etching the SiO 2 from the surface of the heavily doped layer; and r. depositing a layer of electrically conductive material on the surface of the heavily doped layer.
Claim 3
Dependent Claim
51 words
The method recited in claim 1, wherein a thin layer is defined to have a thickness of approximately 0.1 microns (1000 angstroms) or less, a moderate thickness layer is approximately 1 to 5 microns in thickness, and a thick layer is one having a thickness of approximately 100 microns or more.
Claim 4
Dependent Claim
30 words
The method recited in claim 1, wherein the etching in step h is accomplished using an etching solution which does not etch Si 3 N 4 or SiO 2 .
Claim 5
Dependent Claim
27 words
The method recited in claim 1, wherein the etching in steps k and p is accomplished using an etching solution which does not etch SiO 2 .
Claim 6
Independent Claim
281 words
A method of making a silicon epitaxial diode comprising the steps of: a. forming a silicon substrate having a heavily doped layer and a lightly doped layer, both layers being of the first conductivity type; b. thermally growing a layer of SiO 2 on the lightly doped layer; c. depositing a first temporary support layer on the SiO 2 in step b; d. thermally growing a layer of SiO 2 on the heavily doped layer; e. depositing a layer of Si 3 N 4 over the SiO 2 in step d; f. defining a diode pattern on the Si 3 N 4 layer; g. etching through the Si 3 N 4 and the SiO 2 layers in the region outside the diode pattern; h. etching through the lightly and heavily doped layers of silicon to form a mesa-like structure; i. thermally growing a layer of SiO 2 on the sidewalls of the mesa-like structure; j. depositing a second temporary support layer on the SiO 2 in step i; k. removing the first temporary support layer; l. etching the SiO 2 from step b to expose the lightly doped layer; m. introducing dopant of the second conductivity type, opposite the first conductivity type, into the lightly doped layers so as to form a pn junction; n. plating a thick layer of thermally and electrically conductive material on the area doped in step m; o. removing the second temporary support layer; p. etching away the Si 3 N 4 over the diode pattern; q. etching the SiO 2 from the surface of the heavily doped layer; and r. depositing a layer of electrically conductive material on the surface of the heavily doped layer.
Claim 7
Independent Claim
281 words
A method of making a silicon epitaxial diode comprising the steps of: a. forming a silicon substrate having a heavily doped layer and a lightly doped layer, both layers being of the first conductivity type; b. thermally growing a layer of SiO 2 on the lightly doped layer; c. depositing a first temporary support layer on the SiO 2 in step b; d. thermally growing a layer of SiO 2 on the heavily doped layer; e. depositing a layer of Si 3 N 4 over the SiO 2 in step d; f. defining a diode pattern on the Si 3 N 4 layer; g. etching through the Si 3 N 4 and the SiO 2 layers in the region outside the diode pattern; h. etching through the lightly and heavily doped layers of silicon to form a mesa-like structure; i. thermally growing a layer of SiO 2 on the sidewalls of the mesa-like structure; j. depositing a second temporary support layer on the SiO 2 in step i; k. removing the first temporary support layer; l. etching the SiO 2 from step b to expose the lightly doped layer; m. introducing dopant of the second conductivity type, opposite the first conductivity type, into the lightly doped layers so as to form a pn junction; n. plating a thick layer of thermally and electrically conductive material on the area doped in step m; o. removing the second temporary support layer; p. etching away the Si 3 N 4 over the diode pattern; q. etching the SiO 2 from the surface of the heavily doped layer; and r. depositing a layer of electrically conductive material on the surface of the heavily doped layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-14 | 1986-08-16 | 1987-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-14 | 1990-08-16 | 1991-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-14 | 1994-08-16 | 1995-02-15 | $7700.00 | Window Closed / Lapsed |