Method for making electrical contact through an opening of one micron or less for CMOS technology

Claim 1

A method for making electrical contact through an opening of about one micron or less comprising: providing semiconductor device structures in and on a semiconductor substrate; forming an insulating layer structure over said semiconductor device structures; forming a resist mask with at least one substantially vertical sided opening of said one micron or less feature size in the mask over said insulating layer and above the device elements to be electrically contacted thereby exposing said insulating layer; isotropic etching partially through the exposed said insulating layer to a depth of between about 500 to 850 Angstroms to form an undercut region in said insulating layer beneath the edge of said vertical sided opening in said resist mask: thereafter anisotropically etching the remaining thickness of the exposed said insulating layer to complete the construction of a substantially vertical sided opening of a diameter similar to the vertical sided opening in said resist mask through said insulating layer to a device element to be electrically contacted; sputter depositing a metal layer over the exposed surfaces including the bottom of said vertical sided openings, while substantially not depositing said metal upon said vertical sides of said openings; removing said resist mask and said metal thereover by etching with the said break being the attacking point of the resist etching fluid; and depositing a next level metallurgy over the exposed surfaces including said metal remaining in said vertical openings to form said next metallurgy level and to complete said electrical contact.

Claim 2

A method for making electrical contact through an opening of about one micron or less comprising: providing semiconductor device structures in and on a semiconductor substrate; forming an insulating layer structure over said semiconductor device structures; forming a resist mask with at least one substantially vertical sided opening of said one micron or less feature size in the mask over said insulating layer and above the device elements to be electrically contacted thereby exposing said insulating layer; isotropic etching partially through the exposed said insulating layer to a depth of between about 500 to 850 Angstroms to form an undercut region in said insulating layer beneath the edge of said vertical sided opening in said resist mask: thereafter anisotropically etching the remaining thickness of the exposed said insulating layer to complete the construction of a substantially vertical sided opening of a diameter similar to the vertical sided opening in said resist mask through said insulating layer to a device element to be electrically contacted; sputter depositing a metal layer over the exposed surfaces including the bottom of said vertical sided openings, while substantially not depositing said metal upon said vertical sides of said openings; removing said resist mask and said metal thereover by etching with the said break being the attacking point of the resist etching fluid; and depositing a next level metallurgy over the exposed surfaces including said metal remaining in said vertical openings to form said next metallurgy level and to complete said electrical contact.

Claim 12

A method for making electrical contact through an opening of about one micron or less to source/drain regions of a CMOS integrated circuit comprising: providing CMOS semiconductor device structures in and on a semiconductor substrate including said source/drain regions; forming an insulating layer structure over said semiconductor device structures; forming a resist mask with a substantially vertical sided opening of said one micron or less feature size in the mask over said insulating layer and above the said source/drain region to be electrically contacted; isotropic etching partially through the exposed said insulating layer to a depth of between about 500 to 800 Angstroms to form an undercut region in said insulating layer beneath the edge of said vertical sided opening in said resist mask; thereafter anisotropically etching the remaining thickness of the exposed said insulating layer to complete the construction of a substantially vertical sided opening of a diameter similar to the vertical sided opening in said resist mask through said insulating layer to a device element to be electrically contacted; sputter depositing a metal layer over the exposed surfaces including the said source/drain regions at the bottom of said vertical sided openings, while substantially not depositing said metal upon said vertical sides of said openings; removing said resist mask and said metal thereover by etching with the said break being the attacking point of the resist etching fluid; and depositing a next level metallurgy over the exposed surfaces including said metal remaining in said vertical openings to form said next metallurgy level and to complete said electrical contact.

Claim 13

A method for making electrical contact through an opening of about one micron or less to source/drain regions of a CMOS integrated circuit comprising: providing CMOS semiconductor device structures in and on a semiconductor substrate including said source/drain regions; forming an insulating layer structure over said semiconductor device structures; forming a resist mask with a substantially vertical sided opening of said one micron or less feature size in the mask over said insulating layer and above the said source/drain region to be electrically contacted; isotropic etching partially through the exposed said insulating layer to a depth of between about 500 to 800 Angstroms to form an undercut region in said insulating layer beneath the edge of said vertical sided opening in said resist mask; thereafter anisotropically etching the remaining thickness of the exposed said insulating layer to complete the construction of a substantially vertical sided opening of a diameter similar to the vertical sided opening in said resist mask through said insulating layer to a device element to be electrically contacted; sputter depositing a metal layer over the exposed surfaces including the said source/drain regions at the bottom of said vertical sided openings, while substantially not depositing said metal upon said vertical sides of said openings; removing said resist mask and said metal thereover by etching with the said break being the attacking point of the resist etching fluid; and depositing a next level metallurgy over the exposed surfaces including said metal remaining in said vertical openings to form said next metallurgy level and to complete said electrical contact.

Claim 16

A method for making electrical contact through a via opening of about one micron or less from one metallurgy layer to another comprising: providing semiconductor device structures in and on a semiconductor substrate including a metallurgy layer; forming an insulating layer structure over said metallurgy layer; forming a resist mask with a substantially vertical sided opening of said one micron or less feature size in the mask over said insulating layer and above the said metallurgy layer to be electrically contacted; isotropic etching partially through the exposed underlying said insulating layer to a depth of between about 500 to 800 Angstroms to form undercut regions in said insulating layer beneath the edges of said vertical sided openings in said resist mask; thereafter anisotropically etching the remaining thickness of the exposed said insulating layer to complete the construction of said substantially vertical sided openings of a diameter similar to the vertical sided openings in said resist mask through said insulating layer to said metallurgy layer to be electrically contacted; sputter depositing a metal layer over the exposed surfaces including the bottom of said vertical sided openings, while substantially not depositing said metal upon said vertical sides of said openings; removing said resist mask and said metal thereover by etching with the said break being the attacking point of the resist etching fluid; and depositing a next level metallurgy over the exposed surfaces including said metal remaining in said vertical openings to form said next metallurgy level and to complete said electrical contact.

Claim 17

A method for making electrical contact through a via opening of about one micron or less from one metallurgy layer to another comprising: providing semiconductor device structures in and on a semiconductor substrate including a metallurgy layer; forming an insulating layer structure over said metallurgy layer; forming a resist mask with a substantially vertical sided opening of said one micron or less feature size in the mask over said insulating layer and above the said metallurgy layer to be electrically contacted; isotropic etching partially through the exposed underlying said insulating layer to a depth of between about 500 to 800 Angstroms to form undercut regions in said insulating layer beneath the edges of said vertical sided openings in said resist mask; thereafter anisotropically etching the remaining thickness of the exposed said insulating layer to complete the construction of said substantially vertical sided openings of a diameter similar to the vertical sided openings in said resist mask through said insulating layer to said metallurgy layer to be electrically contacted; sputter depositing a metal layer over the exposed surfaces including the bottom of said vertical sided openings, while substantially not depositing said metal upon said vertical sides of said openings; removing said resist mask and said metal thereover by etching with the said break being the attacking point of the resist etching fluid; and depositing a next level metallurgy over the exposed surfaces including said metal remaining in said vertical openings to form said next metallurgy level and to complete said electrical contact.