US4894350A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing ohmic contacts having low transfer resistances
Assignee: Siemens AG
•
Filing: 1988-09-23
•
Granted: 1990-01-16
•
Expires: 2008-09-23
Abstract
Abstract A method for manufacturing ohmic contacts having low transfer resistances on doped semiconductor material, whereby the doping is implanted self-aligning using mask technique and the metallization is applied and, after removal of the mask layer, a temperature-time cycle occurs for simultaneous annealing the doping and alloying in the metallization.
Inventors
- 👤 Hans P. Zwicknagl
- 👤 Helmut Tews
- 👤 Thomas H. Hager
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:36
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10P76/202; H10D; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; Y; Y10; Y10S; Y10S148/00; Y10S148/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
118 words
A method for manufacturing ohmic contacts having low transfer resistances on a semiconductor layer of a III-V semiconductor material, where the semiconductor layer is first provided with a mask layer and an implantation for producing at least one p-doped region, comprising the steps of: (a) applying a metallization onto said semiconductor layer material implanted with said p-doping implantation, the metallization being chosen from the group consisting of: titanium, platinum, and titanium in this sequence; titanium and platinum and gold in this sequence; in this sequence; and germanium, gold, chrome, and gold in this sequence; (b) removing said mask layer and a portion of the metallization situated thereon; and (c) annealing said implantation and alloying in said metallization simultaneously.
Claim 2
Independent Claim
118 words
A method for manufacturing ohmic contacts having low transfer resistances on a semiconductor layer of a III-V semiconductor material, where the semiconductor layer is first provided with a mask layer and an implantation for producing at least one p-doped region, comprising the steps of: (a) applying a metallization onto said semiconductor layer material implanted with said p-doping implantation, the metallization being chosen from the group consisting of: titanium, platinum, and titanium in this sequence; titanium and platinum and gold in this sequence; in this sequence; and germanium, gold, chrome, and gold in this sequence; (b) removing said mask layer and a portion of the metallization situated thereon; and (c) annealing said implantation and alloying in said metallization simultaneously.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said III-V semiconductor material is GaAs.
Claim 4
Dependent Claim
41 words
The method of claim 1 wherein said annealing of said implantation and said alloying in of said metallization is performed by rapid thermal annealing at a temperature of approximately 850° C. to about 900° C. for a maximum of 3 seconds.
References Cited (Backward Citations)
US3769694A
Cited
US4566021A
Cited
US4654960A
Cited
JPS58124276A
Cited
JPS58145158A
Cited
US4472206A
Cited
JPS59111325A
Cited
US4574298A
Cited
US4471005A
Cited
EP0123926A2
Cited
EP0128385A2
Cited
US4470189A
Cited
US4570324A
Cited
US4610730A
Cited
US4679305A
Cited
US4729967A
Cited
EP0303079A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |