Patent US5265234A successfully refreshed from Google Patents.
US5265234A
Expired / Lapsed
US
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Integrated memory circuit and function unit with selective storage of logic functions
Assignee: Hitachi Ltd
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Filing: 1993-01-29
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Granted: 1993-11-23
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Expires: 2013-01-29
Abstract
Abstract In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in read-modify-write mode can be used commonly.
Inventors
- 👤 Toshihiko Ogura
- 👤 Hiroaki Aotsu
- 👤 Koichi Kimura
- 👤 Hiromichi Enomoto
- 👤 Tadashi Kyoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:24
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393; G09G2340/00; G09G2340/10
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
153 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element capable of operating in normal operation modes for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals supplied through said control terminal; operation mode storing means for storing signals, transferred from said address terminal and representing an operation mode for operating on data to be written in said memory element, in response to a combination of said control signals other than one of said predetermined combinations of said control signals corresponding to a normal operation mode; and means for transferring data to or from said memory element in accordance with said operation mode stored in said operation mode storing means only after said operation mode has been set in said operation mode storing means.
Claim 2
Dependent Claim
153 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element capable of operating in normal operation modes for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals supplied through said control terminal; operation mode storing means for storing signals, transferred from said address terminal and representing an operation mode for operating on data to be written in said memory element, in response to a combination of said control signals other than one of said predetermined combinations of said control signals corresponding to a normal operation mode; and means for transferring data to or from said memory element in accordance with said operation mode stored in said operation mode storing means only after said operation mode has been set in said operation mode storing means.
Claim 3
Dependent Claim
27 words
A memory device according to claim 1, wherein said control signals include a write enable signal, a row address strobe signal, and a column address strobe signal.
Claim 4
Dependent Claim
22 words
A memory device according to claim 1, wherein said operation mode storing means receives said operation mode signals through said address terminal.
Claim 5
Dependent Claim
29 words
A memory device according to claim 1, wherein said operation mode storing means receives said operation mode as lower bits of an address signal received through said address terminal.
Claim 6
Dependent Claim
24 words
A memory device according to claim 1, wherein said address signals supplied through said address terminal include row address signals and column address signals.
Claim 7
Dependent Claim
153 words
An operation mode setting method for setting an operation mode for operating on data to be written in a memory device having a data terminal, an address terminal, a control terminal and a memory element capable of operating in memory operation modes for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals supplied through said control terminal, comprising the steps of: (a) setting a write enable signal at an active level; (b) setting a row address strobe signal at an active level subsequent to said step (a); (c) storing an operation mode for operating on data to be written in said memory device in response to said step (b); and (d) accessing said memory element in accordance with said operation mode stored in step (c) subsequent to completion of said step (c).
Claim 8
Dependent Claim
153 words
An operation mode setting method for setting an operation mode for operating on data to be written in a memory device having a data terminal, an address terminal, a control terminal and a memory element capable of operating in memory operation modes for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals supplied through said control terminal, comprising the steps of: (a) setting a write enable signal at an active level; (b) setting a row address strobe signal at an active level subsequent to said step (a); (c) storing an operation mode for operating on data to be written in said memory device in response to said step (b); and (d) accessing said memory element in accordance with said operation mode stored in step (c) subsequent to completion of said step (c).
Claim 9
Dependent Claim
23 words
An operation mode setting method according to claim 6, wherein said operation mode stored in step (c) is received through said address terminal.
Claim 10
Dependent Claim
160 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element capable of operating in memory operation modes for reading, writing and holding data from, to and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals which include a write enable signal and a row address strobe signal supplied through said control terminal; operation mode storing means, responsive to a combination of said control signals other than one of said predetermined combinations, for storing signals, transferred from said address terminal and representing an operation mode other than a memory operation mode, for operating on data to be written in said memory element; and means for transferring data, to or from said memory element in accordance with an operation mode stored in said operation mode storing means only after said operation mode has been stored in said operation mode storing means.
Claim 11
Dependent Claim
160 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element capable of operating in memory operation modes for reading, writing and holding data from, to and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals which include a write enable signal and a row address strobe signal supplied through said control terminal; operation mode storing means, responsive to a combination of said control signals other than one of said predetermined combinations, for storing signals, transferred from said address terminal and representing an operation mode other than a memory operation mode, for operating on data to be written in said memory element; and means for transferring data, to or from said memory element in accordance with an operation mode stored in said operation mode storing means only after said operation mode has been stored in said operation mode storing means.
Claim 12
Dependent Claim
47 words
A memory device according to claim 8, wherein said combination of said control signals to which said operation mode storing means is responsive is the combination in which the write enable strobe signal becomes an active level before a row address strobe signal becomes an active level.
Claim 13
Dependent Claim
160 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element capable of operating in normal memory operation modes for reading, writing and holding data from, to and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combination of states of control signals supplied through said control terminal; an operation mode storing means, responsive to a combination of states of said control signals other than one of said predetermined combinations of states, for storing signals, transferred from said address terminal and representing an operation mode other than a normal memory operation mode, for operating on data to be written in said memory element; and a data transfer line for transferring data to, or from said memory element in accordance with an operation mode stored in said operation mode storing means only after said operation mode has been set in said operation mode storing means.
Claim 14
Dependent Claim
160 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element capable of operating in normal memory operation modes for reading, writing and holding data from, to and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combination of states of control signals supplied through said control terminal; an operation mode storing means, responsive to a combination of states of said control signals other than one of said predetermined combinations of states, for storing signals, transferred from said address terminal and representing an operation mode other than a normal memory operation mode, for operating on data to be written in said memory element; and a data transfer line for transferring data to, or from said memory element in accordance with an operation mode stored in said operation mode storing means only after said operation mode has been set in said operation mode storing means.
Claim 15
Dependent Claim
118 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and memory control signals supplied through said control terminal; operation mode storing means responsive to a predetermined combination of states of said memory control signals for storing signals transferred from said address terminal representing an operation mode for operating on data to be written in said memory element; and means for transferring data to or from said memory element in accordance with an operation mode represented by signals stored in said operation mode storing means.
Claim 16
Dependent Claim
118 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and memory control signals supplied through said control terminal; operation mode storing means responsive to a predetermined combination of states of said memory control signals for storing signals transferred from said address terminal representing an operation mode for operating on data to be written in said memory element; and means for transferring data to or from said memory element in accordance with an operation mode represented by signals stored in said operation mode storing means.
Claim 17
Dependent Claim
28 words
A memory device according to claim 11, wherein said memory control signals include a write enable signal, a row address strobe signal, and a column address strobe signal.
Claim 18
Dependent Claim
31 words
A memory device according to claim 11, wherein said operation mode storing means receives said signals representing an operation mode as lower bits of a signal received through said address terminal.
Claim 19
Dependent Claim
36 words
A memory device according to claim 11, wherein said combination of memory control signals includes a low level write enable signal and a transition of a row address strobe signal from high level to low level.
Claim 20
Dependent Claim
161 words
An operation mode setting method for setting an operation mode for operating on data to be written in a memory device having a data terminal, an address terminal, a control terminal and a memory element capable of operating in normal operation modes for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals supplied through said control terminal, comprising the steps of: storing signals, transferred from said address terminal and representing an operation mode for operating on data to be written in said memory element, in response to a combination of said control signals other than one of said predetermined combinations of said control signals corresponding to a normal operation mode; and transferring data to or from said memory element in accordance with said stored signals representing an operation mode only after said signals representing said operation mode have been stored.
Claim 21
Dependent Claim
161 words
An operation mode setting method for setting an operation mode for operating on data to be written in a memory device having a data terminal, an address terminal, a control terminal and a memory element capable of operating in normal operation modes for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals supplied through said control terminal, comprising the steps of: storing signals, transferred from said address terminal and representing an operation mode for operating on data to be written in said memory element, in response to a combination of said control signals other than one of said predetermined combinations of said control signals corresponding to a normal operation mode; and transferring data to or from said memory element in accordance with said stored signals representing an operation mode only after said signals representing said operation mode have been stored.
Claim 22
Dependent Claim
26 words
A method according to claim 15, wherein said control signals include a write enable signal, a row address strobe signal, and a column address strobe signal.
Claim 23
Dependent Claim
26 words
A method according to claim 15, wherein said signals representing said operation mode are received as lower bits of a signal applied to said address terminal.
Claim 24
Dependent Claim
22 words
A method according to claim 15, wherein said signals supplied through said address terminal include row address signals and column address signals.
Claim 25
Dependent Claim
153 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element capable of operating in normal operation modes for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals supplied through said control terminal; an operation mode storage for storing signals, transferred from said address terminal and representing an operation mode for operating on data to be written in said memory element, in response to a combination of said control signals other than one of said predetermined combinations of said control signals corresponding to a normal operation mode; and a circuit for transferring line data to or from said memory element in accordance with said operation mode stored in said operation mode storage only after said operation mode has been set in said operation mode storage.
Claim 26
Dependent Claim
153 words
A memory device having a data terminal, an address terminal, and a control terminal, comprising: a memory element capable of operating in normal operation modes for reading, writing and holding data from, to, and in a plurality of storage locations in response to address signals supplied through said address terminal and predetermined combinations of control signals supplied through said control terminal; an operation mode storage for storing signals, transferred from said address terminal and representing an operation mode for operating on data to be written in said memory element, in response to a combination of said control signals other than one of said predetermined combinations of said control signals corresponding to a normal operation mode; and a circuit for transferring line data to or from said memory element in accordance with said operation mode stored in said operation mode storage only after said operation mode has been set in said operation mode storage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |