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US5262342A
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Method of making a semiconductor memory device having error checking/correcting functions
Assignee: Mitsubishi Electric Corp
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Filing: 1991-10-07
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Granted: 1993-11-16
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Expires: 2011-10-07
Abstract
Abstract A semiconductor memory device having error checking/correcting functions includes a circuit (10) for generating a code for error checking/correcting based on information externally supplied and linking the information and the code to be transmitted to a memory cell array (1), and another circuit (11) for error checking and correcting read-out information from the information and the code which are read-out from the memory cell array so as to output correct read-out information. The code word generating circuit (10) and the error checking/correcting circuit (11) are formed of a masked ROM integrated on the same semiconductor chip (100) as that of the memory cell array (1) in the memory device.
Inventors
- 👤 Tsuyoshi Toyama
- 👤 Shinichi Kobayashi
- 👤 Kenji Noguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:00
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
188 words
A method of making a non-volatile memory including a floating gate type memory cell, and a masked ROM including an insulated gate type transistor cell for storing fixed data, comprising the steps of: forming a gate insulation layer on a substrate in the same manufacturing step for said floating gate type memory cell and said insulated gate type transistor cell, forming a floating gate layer for said floating gate type memory cell on said gate insulation layer, forming a second insulation layer on said floating gate layer, forming a control gate electrode layer on said second insulation layer for said floating gate type memory cell, and forming a gate electrode for said insulated gate type transistor cell in the same manufacturing step with forming of one of either said floating gate layer and said control gate electrode layer, wherein said step of forming a gate electrode includes a step of forming an additional insulation layer on said gate insulation layer in the same manufacturing step with forming said second insulation layer when the gate electrode is formed in the same manufacturing step with forming the control gate layer.
Claim 2
Independent Claim
188 words
A method of making a non-volatile memory including a floating gate type memory cell, and a masked ROM including an insulated gate type transistor cell for storing fixed data, comprising the steps of: forming a gate insulation layer on a substrate in the same manufacturing step for said floating gate type memory cell and said insulated gate type transistor cell, forming a floating gate layer for said floating gate type memory cell on said gate insulation layer, forming a second insulation layer on said floating gate layer, forming a control gate electrode layer on said second insulation layer for said floating gate type memory cell, and forming a gate electrode for said insulated gate type transistor cell in the same manufacturing step with forming of one of either said floating gate layer and said control gate electrode layer, wherein said step of forming a gate electrode includes a step of forming an additional insulation layer on said gate insulation layer in the same manufacturing step with forming said second insulation layer when the gate electrode is formed in the same manufacturing step with forming the control gate layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-15 | 1997-05-17 | 1997-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-15 | 2001-05-17 | 2001-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-15 | 2005-05-17 | 2005-11-16 | $7700.00 | Window Closed / Lapsed |