Patent US5258637A successfully refreshed from Google Patents.
US5258637A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor devices produced according to a method which reduces contact resistance at silicide/active area interfaces
Assignee: Micron Technology Inc
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Filing: 1992-03-11
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Granted: 1993-11-02
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Expires: 2012-03-11
Abstract
Abstract Disclosed is a semiconductor processing method for reducing contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide. The method comprises implanting germanium through the contact opening and into the active area of the wafer to a peak density at an elevation which is at or above the elevation of the peak density of the conductivity enhancing impurity. A layer of metal is applied atop the wafer and into the contact opening to contact the active area. The metal and silicon within the contact opening are annealed to form a metal silicide. The annealing step consumes elemental silicon into the wafer to an elevation which is at or above the elevation of the germanium peak density. The germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal.
Inventors
- 👤 Gurtej S. Sandhu
- 👤 Mohammed Anjum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:48
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/01125; H10D64/025; H10P30/208; H10P30/225; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10W20/047; H10W20/071; H10W20/081; H10W20/40
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
414 words
Integrated circuitry having reduced contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide, the integrated circuitry being produced according to a method comprising the following steps: providing field oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area, the first type conductivity implanting occurring after provision of the field oxide regions; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, the second elevation being from about 750 Angstroms to about 1500 Angstroms from the starting upper silicon surface b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; after annealing the active area, implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and after implanting the germanium, annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the fourth elevation being from about 100 Angstroms to about 400 Angstroms from the starting upper silicon surface, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 2
Dependent Claim
414 words
Integrated circuitry having reduced contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide, the integrated circuitry being produced according to a method comprising the following steps: providing field oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area, the first type conductivity implanting occurring after provision of the field oxide regions; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, the second elevation being from about 750 Angstroms to about 1500 Angstroms from the starting upper silicon surface b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; after annealing the active area, implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and after implanting the germanium, annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the fourth elevation being from about 100 Angstroms to about 400 Angstroms from the starting upper silicon surface, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 3
Dependent Claim
389 words
Integrated circuitry produced according to a method comprising the following sequential steps: providing field oxide and gate oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; applying a layer of polysilicon atop the wafer and patterning the polysilicon layer to form polysilicon gates atop the gate oxide regions; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, the second elevation being from about 750 Angstroms to about 1500 Angstroms from the starting upper silicon surface b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the fourth elevation being from about 100 Angstroms to about 400 Angstroms from the starting upper silicon surface, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 4
Dependent Claim
389 words
Integrated circuitry produced according to a method comprising the following sequential steps: providing field oxide and gate oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; applying a layer of polysilicon atop the wafer and patterning the polysilicon layer to form polysilicon gates atop the gate oxide regions; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, the second elevation being from about 750 Angstroms to about 1500 Angstroms from the starting upper silicon surface b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the fourth elevation being from about 100 Angstroms to about 400 Angstroms from the starting upper silicon surface, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 5
Dependent Claim
378 words
Integrated circuitry having reduced contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide, the integrated circuitry being produced according to a method comprising the following steps: providing field oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area, the first type conductivity implanting occurring after provision of the field oxide regions; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; after annealing the active area, implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and after implanting the germanium, annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 6
Dependent Claim
378 words
Integrated circuitry having reduced contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide, the integrated circuitry being produced according to a method comprising the following steps: providing field oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area, the first type conductivity implanting occurring after provision of the field oxide regions; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; after annealing the active area, implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and after implanting the germanium, annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 7
Dependent Claim
396 words
Integrated circuitry having reduced contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide, the integrated circuitry being produced according to a method comprising the following steps: providing field oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area, the first type conductivity implanting occurring after provision of the field oxide regions; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; after annealing the active area, implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and after implanting the germanium, annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the fourth elevation being from about 100 Angstroms to about 400 Angstroms from the starting upper silicon surface, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 8
Dependent Claim
396 words
Integrated circuitry having reduced contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide, the integrated circuitry being produced according to a method comprising the following steps: providing field oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area, the first type conductivity implanting occurring after provision of the field oxide regions; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; after annealing the active area, implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and after implanting the germanium, annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the fourth elevation being from about 100 Angstroms to about 400 Angstroms from the starting upper silicon surface, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 9
Dependent Claim
396 words
Integrated circuitry having reduced contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide, the integrated circuitry being produced according to a method comprising the following steps: providing field oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area, the first type conductivity implanting occurring after provision of the field oxide regions; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, the second elevation being from about 750 Angstroms to about 1500 Angstroms from the starting upper silicon surface b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; after annealing the active area, implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and after implanting the germanium, annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 10
Dependent Claim
396 words
Integrated circuitry having reduced contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide, the integrated circuitry being produced according to a method comprising the following steps: providing field oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area, the first type conductivity implanting occurring after provision of the field oxide regions; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, the second elevation being from about 750 Angstroms to about 1500 Angstroms from the starting upper silicon surface b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; after annealing the active area, implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and after implanting the germanium, annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 11
Dependent Claim
353 words
Integrated circuitry produced according to a method comprising the following sequential steps: providing field oxide and gate oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; applying a layer of polysilicon atop the wafer and patterning the polysilicon layer to form polysilicon gates atop the gate oxide regions; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 12
Dependent Claim
353 words
Integrated circuitry produced according to a method comprising the following sequential steps: providing field oxide and gate oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; applying a layer of polysilicon atop the wafer and patterning the polysilicon layer to form polysilicon gates atop the gate oxide regions; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 13
Dependent Claim
371 words
Integrated circuitry produced according to a method comprising the following sequential steps: providing field oxide and gate oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; applying a layer of polysilicon atop the wafer and patterning the polysilicon layer to form polysilicon gates atop the gate oxide regions; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the fourth elevation being from about 100 Angstroms to about 400 Angstroms from the starting upper silicon surface, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 14
Dependent Claim
371 words
Integrated circuitry produced according to a method comprising the following sequential steps: providing field oxide and gate oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; applying a layer of polysilicon atop the wafer and patterning the polysilicon layer to form polysilicon gates atop the gate oxide regions; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the fourth elevation being from about 100 Angstroms to about 400 Angstroms from the starting upper silicon surface, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 15
Dependent Claim
371 words
Integrated circuitry produced according to a method comprising the following sequential steps: providing field oxide and gate oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; applying a layer of polysilicon atop the wafer and patterning the polysilicon layer to form polysilicon gates atop the gate oxide regions; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, the second elevation being from about 750 Angstroms to about 1500 Angstroms from the starting upper silicon surface, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 16
Dependent Claim
371 words
Integrated circuitry produced according to a method comprising the following sequential steps: providing field oxide and gate oxide regions atop a silicon wafer, the silicon wafer having a starting upper silicon surface; applying a layer of polysilicon atop the wafer and patterning the polysilicon layer to form polysilicon gates atop the gate oxide regions; implanting a first type conductivity enhancing impurity into the silicon wafer to a first peak density at a first elevation relative to the starting upper silicon surface to define an active area; post-implant annealing the active area to, a) transform the first peak density at the first elevation into a second peak density at a second elevation relative to the starting upper silicon surface, the second peak density being less than the first peak density, the second elevation being below the first elevation, the second elevation being from about 750 Angstroms to about 1500 Angstroms from the starting upper silicon surface, b) repair crystal damage imparted to the wafer the result of the implant, and c) electrically enable the active area; providing a layer of insulating dielectric atop the wafer; selectively patterning and etching the insulating dielectric to provide a contact opening to the active area, the contact opening upwardly exposing only a portion of the silicon of the active area; implanting germanium through the contact opening and into the active area of the wafer to a third peak density at a third elevation relative to the starting upper silicon surface, the third elevation being at or above the second elevation, the third elevation being from about 250 Angstroms to about 850 Angstroms from the starting upper silicon surface; applying a layer of metal atop the wafer and into the contact opening to contact the active area, the metal within the contact engaging an upper surface of the silicon of the active area; and annealing the metal and silicon within the contact opening to form a metal silicide; the annealing step consuming elemental silicon into the wafer to a fourth elevation relative to the starting upper silicon surface in formation of the silicide, the fourth elevation being at or above the third elevation, the germanium restricting diffusion of the conductivity enhancing impurity therethrough during the silicide annealing.
Claim 17
Dependent Claim
145 words
An electronic component of integrated circuitry formed within a silicon semiconductor substrate comprising: an electrically enabled active area formed within the silicon substrate, the active area having an uppermost surface, the active area comprising a first type conductivity enhancing impurity having a dopant peak density at an active area elevation from the uppermost surface; the active area including a region of germanium atoms having a dopant peak density at a germanium elevation from the uppermost surface and within the active area, the germanium elevation being at or above the active area elevation; and a region of metal silicide projecting into the active area from the active area upper surface, the region of metal silicide having a terminus base positioned within the active area at a silicide elevation, the terminus base silicide elevation being from about 150 Angstroms to about 450 Angstroms above the germanium elevation.
Claim 18
Dependent Claim
145 words
An electronic component of integrated circuitry formed within a silicon semiconductor substrate comprising: an electrically enabled active area formed within the silicon substrate, the active area having an uppermost surface, the active area comprising a first type conductivity enhancing impurity having a dopant peak density at an active area elevation from the uppermost surface; the active area including a region of germanium atoms having a dopant peak density at a germanium elevation from the uppermost surface and within the active area, the germanium elevation being at or above the active area elevation; and a region of metal silicide projecting into the active area from the active area upper surface, the region of metal silicide having a terminus base positioned within the active area at a silicide elevation, the terminus base silicide elevation being from about 150 Angstroms to about 450 Angstroms above the germanium elevation.
References Cited (Backward Citations)
US4835112A
Cited
US5156994A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-01 | 1997-05-03 | 1997-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-01 | 2001-05-03 | 2001-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-01 | 2005-05-03 | 2005-11-02 | $7700.00 | Window Closed / Lapsed |