Self-aligned conducting etch stop for interconnect patterning

Claim 1

A process for fabricating an interconnect for a semiconductor structure, comprising the steps of: depositing a conductive etch stop layer on a structure; depositing a sacrificial alloying layer on said conductive etch stop layer, and depositing an interconnect layer on the sacrificial alloying layer, said conductive etch stop layer having etch selectivity to said sacrificial alloying layer and said interconnect layer; etching said sacrificial alloying layer and said interconnect layer, stopping on said conductive etch stop layer, so as to form an interconnect from said interconnect layer; reacting said conductive etch stop layer with said sacrificial alloying layer so as to form a metal alloy which electrically connects said interconnect with said structure, wherein portions of said conductive etch stop layer not in contact with said interconnect do not react; and etching and removing the portions of said conductive etch stop layer which do not react.