Random access memory device having transfer gate unit for blocking flash write data buffer unit from parasitic capacitance coupled with bit line pairs of memory cells

Claim 1

A random access memory device selectively entering a usual write-in phase, a usual read-out phase and a flash write phase of operation, comprising: a) a plurality of random access memory cells arranged in rows and columns, and respectively storing data bits; b) a plurality of first bit line pairs respectively coupled with the columns of said random access memory cells; c) a plurality of word lines respectively coupled with the rows of said random access memory cells, and selectively activated for allowing data bits to be read out from random access memory cells coupled therewith to the associated first bit line pairs in the form of small differential voltage level, said word lines being further operative to allow data bits respectively indicated by large differential voltage levels on said plurality of first bit line pairs to be written into said random access memory cells coupled therewith; d) a plurality of second bit line pairs respectively associated with said plurality of first bit line pairs; e) a plurality of sense amplifier circuits respectively coupled with said plurality of second bit line pairs, and activated for respectively developing small differential voltage levels into said large differential voltage levels; f) a first transfer gate unit coupled between said plurality of first bit line pairs and said plurality of second bit line pairs, and responsive to a timing controlling signal for interconnecting said plurality of first bit line pairs and said plurality of second bit line pairs; g) a flash write data buffer unit responsive to a flash write data bit for producing a small differential voltage level on a flash write data bus; h) a second transfer gate unit coupled between said flash write data bus and said plurality of second bit line pairs, and responsive to a gate control signal for distributing said small differential voltage level indicative of said flash write data bit to said plurality of second bit line pairs in said flash write phase of operation; and i) a timing controller for producing said timing controlling signal, said timing controlling signal causing said first transfer gate unit to interconnect said plurality of first bit line pairs and said plurality of second bit line pairs except for a first predetermined time period containing at least a time period between activation of said sense amplifier circuits and completion of development into said large differential voltage levels in said usual read-out phase, said timing controlling signal causing said first transfer gate unit to interconnect said plurality of first bit line pairs and said plurality of second bit line pairs except for a second time period containing at least a time period between transmission of said small differential voltage level to said plurality of second bit line pairs and completion of development into said large differential voltage levels in said flash write phase.