Patent US5255229A successfully refreshed from Google Patents.
US5255229A
Expired / Lapsed
US
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Dynamic random access memory including stress test circuitry
Assignee: Toshiba Corp
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Filing: 1991-12-26
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Granted: 1993-10-19
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Expires: 2011-12-26
Abstract
Abstract A dynamic random access memory according to the present invention comprises a voltage stress test pad to which a stress voltage is externally applied when a voltage stress test is carried out, transistors which turn off when the stress voltage is not applied to the voltage stress test pad and which, when the stress voltage is applied thereto, transmit the stress voltage to more word lines than those selected in response to an external address signal in a normal operation mode, and a noise killer control circuit for turning off a noise killer circuit connected to a word line to which the stress voltage is applied when the voltage stress test is carried out.
Inventors
- 👤 Hiroaki Tanaka
- 👤 Masaru Koyanagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/50; G11C11/401
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
231 words
A dynamic random access memory, comprising: a plurality of memory cells arranged in rows and columns; a word line connected to the memory cells in the same row; a bit line connected to the memory cells in the same column; a word line selection circuit for generating a word line selection signal in response to an address signal; a word line driving circuit, connected between a word line driving voltage source and said word line, for driving said word line in response to an output signal of said word line selection circuit; a noise killer circuit connected between said word line and ground potential; a voltage stress test terminal to which a stress voltage is externally applied during a voltage stress test; stress voltage transmission means, coupled to a first predetermined number of word lines and to the voltage stress test terminal for transmitting the stress voltage to the first predetermined number of word lines which is greater than a second predetermined number of word lines selected in response to the address signal during a normal operation mode when the stress voltage is applied to said voltage stress terminal and noise killer control means coupled to the noise killer circuit and responsive to a first control signal for turning off said noise killer circuit connected to said word line to which the stress voltage is applied during the voltage stress test.
Claim 2
Dependent Claim
231 words
A dynamic random access memory, comprising: a plurality of memory cells arranged in rows and columns; a word line connected to the memory cells in the same row; a bit line connected to the memory cells in the same column; a word line selection circuit for generating a word line selection signal in response to an address signal; a word line driving circuit, connected between a word line driving voltage source and said word line, for driving said word line in response to an output signal of said word line selection circuit; a noise killer circuit connected between said word line and ground potential; a voltage stress test terminal to which a stress voltage is externally applied during a voltage stress test; stress voltage transmission means, coupled to a first predetermined number of word lines and to the voltage stress test terminal for transmitting the stress voltage to the first predetermined number of word lines which is greater than a second predetermined number of word lines selected in response to the address signal during a normal operation mode when the stress voltage is applied to said voltage stress terminal and noise killer control means coupled to the noise killer circuit and responsive to a first control signal for turning off said noise killer circuit connected to said word line to which the stress voltage is applied during the voltage stress test.
Claim 3
Dependent Claim
62 words
The dynamic random access memory according to claim 1, further comprising a bit line precharge circuit connected between said bit line and a bit line precharge power line and controlled in response to a second control signal, and a bit line precharge voltage generation circuit for generating a bit line precharge voltage which is applied to said bit line precharge power line.
Claim 4
Dependent Claim
32 words
The dynamic random access memory according to claim 2, further comprising bit line potential control means for controlling a potential of said bit line precharge power line during the voltage stress test.
Claim 5
Dependent Claim
59 words
The dynamic random access memory according to claim 3, wherein the first control signal which controls said nose killer control means is one of a control signal of said bit line potential control means, a control signal depending on the stress voltage applied to said voltage stress test terminal, or a signal used by said stress voltage transmission means.
Claim 6
Dependent Claim
72 words
The dynamic random access memory according to claim 2, wherein the first control signal which controls said nose killer control means is one of a control signal of a bit line potential control means wherein the bit line potential control means is coupled to the bit line, a control signal depending on the stress voltage applied to said voltage stress test terminal, or a signal used by said stress voltage transmission means.
Claim 7
Dependent Claim
58 words
The dynamic random access memory according to claim 1, further comprising bit line potential control means, coupled to a bit line precharge power line and responsive to a third control signal, for controlling a potential of said bit line precharge power line during the voltage stress test, said bit line precharge power line coupled to the bit line.
Claim 8
Dependent Claim
59 words
The dynamic random access memory according to claim 6, wherein the first control signal which controls said noise killer control means is one of a control signal of said bit line potential control means, a control signal depending on the stress voltage applied to said voltage stress test terminal, or a signal used by said stress voltage transmission means.
Claim 9
Dependent Claim
72 words
The dynamic random access memory according to claim 1, wherein the first control signal which controls said noise killer control means is one of a control signal of a bit line potential control means wherein the bit line potential control means is coupled to the bit line, a control signal depending on the stress voltage applied to said voltage stress test terminal, or a signal used by said stress voltage transmission means.
Claim 10
Dependent Claim
79 words
The dynamic random access memory according to any one of claim 6 7 or 8, wherein during the voltage stress test, said bit line potential control means controls an output of a bit line precharge voltage generation circuit to be in an OFF-state for permitting an externally input bit line potential to be applied to said bit line precharge power line or for permitting said bit line precharge power line to be connected to a predetermined fixed potential terminal.
Claim 11
Dependent Claim
101 words
The dynamic random access memory according to claim 9, further comprising a plate potential generation circuit, coupled to a capacitor plate of a memory cell of the plurality of memory cells, for generating a plate potential which is applied to the capacitor plate of said memory cell, and plate potential control means, responsive to one of a control signal of said bit line potential control means, a control signal depending on the stress voltage applied to said voltage stress test terminal, or a signal used by said stress voltage transmission means, for controlling an output of the plate potential generation circuit.
Claim 12
Dependent Claim
67 words
The dynamic random access memory according to claim 10, wherein during the voltage stress test, said plate potential control means controls an output of said plate potential generation circuit to be in an OFF-state for permitting an externally input plate potential to be applied to the capacitor plate of said memory cell or for permitting said capacitor plate to be connected to a predetermined fixed potential terminal.
Claim 13
Dependent Claim
106 words
The dynamic random access memory according to any one of claims 6 to 4, further comprising a plate potential generation circuit, coupled to a capacitor plate of a memory cell of the plurality of memory cells, for generating a plate potential which is applied to the capacitor plate of said memory cell, and plate potential control means, responsive to one of a control signal of said bit line potential control means, a control signal depending on the stress voltage applied to said voltage stress test terminal or a signal used by said stress voltage transmission means, for controlling an output of the plate potential generation circuit.
Claim 14
Dependent Claim
67 words
The dynamic random access memory according to claim 12, wherein during the voltage stress test, said plate potential control means controls an output of said plate potential generation circuit to be in an OFF-state for permitting an externally input plate potential to be applied to the capacitor plate of said memory cell or for permitting said capacitor plate to be connected to a predetermined fixed potential terminal.
Claim 15
Dependent Claim
73 words
The dynamic random access memory according to any one of claim 3, 4 or 5, wherein during the voltage stress test, said bit line potential control means controls an output of the bit line precharge voltage generation circuit in an OFF-state permitting an externally input bit line potential to be applied to said bit line precharge power line or to connect said bit line precharge power line to a predetermined fixed potential terminal.
Claim 16
Dependent Claim
29 words
The dynamic random access memory according to claim 1, wherein said first control signal is produced in accordance with the stress voltage applied to said voltage stress test terminal.
Claim 17
Dependent Claim
22 words
The dynamic random access memory according to claim 1, wherein said first control signal is applied to said stress voltage transmission means.
Claim 18
Dependent Claim
47 words
The dynamic random access memory according to claim 1, further comprising a capacitor plate, a plate potential generation circuit for generating a plate potential applied to capacitor plates of said memory cells, and plate potential control means for setting potentials of said capacitor plates at desired values.
Claim 19
Dependent Claim
110 words
The dynamic random access memory according to claim 17, wherein said plate potential control means comprises a plate potential application pad connected to said capacitor plates, and to which a desired plate potential is externally applied during the voltage stress test, and an output switching circuit between an output terminal of said plate potential generation circuit and said capacitor plates, and an output switching control circuit for turning on said output switching circuit during a normal operation time, and turning off said output switching circuit during the voltage stress test in response to said first control signal which is applied to said output switching circuit during the voltage stress test.
Claim 20
Dependent Claim
95 words
The dynamic random access memory according to claim 17, wherein said plate potential control means comprises an output switching circuit between an output terminal of said plate potential generation circuit and said capacitor plates, and a control circuit for turning on said output switching circuit during a normal operation, and turning off said output switching circuit and connecting said capacitor said capacitor plates to a predetermined fixed potential terminal during the voltage stress test in response to said first control signal which is applied to said output switching circuit during the voltage stress test time.
Claim 21
Dependent Claim
113 words
The dynamic random access memory according to claim 1, further comprising a bit line precharge power line for applying a precharge voltage to said bit line, a bit line precharge voltage generation circuit for generating a bit line precharge voltage to be applied to said bit line precharge power line, and a bit line potential control means, connected to said bit line precharge power line, for setting a potential of said bit line precharge power line, for setting a potential of said bit line precharge power line at a desired value in response to said first control signal which is applied to said bit line potential control means during the voltage stress test.
Claim 22
Dependent Claim
134 words
The dynamic random access memory according to claim 20, wherein said bit line potential control means comprises a bit line potential application pad to which a bit line potential is externally applied during the voltage stress test, an output switching circuit between an output terminal of said bit line precharge voltage generation circuit and said bit line precharge power line, a bit line potential control signal application pad to which a bit line potential control signal is applied externally during the voltage stress test, an output switch control circuit for turning on said output switching circuit during a normal operation, and turning off said output switching circuit during the voltage stress test in response to said bit potential control signal which is applied to said output switch control circuit during the voltage stress test.
Claim 23
Dependent Claim
120 words
The dynamic random access memory according to claim 20, further comprising an output switching circuit between an output terminal of said bit line precharge voltage generation and said bit line precharge power line, a bit line potential control signal application pad to which a bit line potential control signal is applied externally during the voltage stress test, and a control circuit for turning on said output switching circuit during a normal operation time, and turning off said output switching circuit and connecting said bit line precharge power line to a predetermined fixed potential terminal during the voltage stress test in response to said bit line potential control signal which is applied to said control circuit during the voltage stress test.
Claim 24
Dependent Claim
71 words
The dynamic random access memory according to claim 20, further comprising a plate potential circuit for generating plate potential to be applied to said capacitor plates of said memory cells, and plate potential control means, connected to said capacitor, for setting potentials of said capacitor plates at desired values on the basis of a second control signal which is applied to said plate potential control means during the voltage stress test.
Claim 25
Dependent Claim
98 words
The dynamic random access memory according to claim 23, wherein said plate potential control means comprises a plate potential application pad to which a desired plate potential is applied externally during the voltage stress test, and an output switching circuit which is inserted between an output terminal of said plate potential generation circuit and said capacitor plates, and an output circuit for turning on said output switching circuit during a normal operation, and turning off said output switching circuit during the voltage stress test time in response to a control signal of said bit line potential control means.
Claim 26
Dependent Claim
84 words
The dynamic random access memory according to claim 23, said plate potential control means comprises an output switching circuit between an output terminal of said plate potential generation circuit and said capacitor plates, and an output circuit for turning on said output switching circuit during a normal operation, and turning off said output switching circuit and connecting said capacitor plate to a predetermined fixed potential terminal during the voltage stress test in response to a control signal of said bit line potential control means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-18 | 1997-04-19 | 1997-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-18 | 2001-04-19 | 2001-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-18 | 2005-04-19 | 2005-10-19 | $7700.00 | Window Closed / Lapsed |