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US5253197A
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US
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Semiconductor associative memory device with current sensing
Assignee: Hitachi Ltd
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Filing: 1990-09-11
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Granted: 1993-10-12
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Expires: 2010-09-11
Abstract
Abstract In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.
Inventors
- 👤 Makoto Suzuki
- 👤 Suguru Tachibana
- 👤 Hisayuki Higuchi
- 👤 Katsuhiro Shimohigashi
- 👤 Takehisa Hayashi
- 👤 Makoto Hanawa
- 👤 Tadahiko Nishimukai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:08
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0895; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
163 words
A semiconductor memory device, comprising: a plurality of memory cells for storing information; and a plurality of comparator circuits each of which being coupled for respectively comparing units of information stored in ones of said plurality of memory cells with comparison input information, corresponding to each unit of the information, and outputting a result of each comparison, wherein readout currents from ones of said plurality of memory cells being read out are respectively supplied to corresponding ones of said plurality of comparator circuits without first being converted into a voltage, wherein each one of said plurality of comparator circuits provides a comparison operation of readout current from a selected one of corresponding ones of said plurality of memory cells with comparison input information supplied thereto, and wherein each of the comparator circuits includes a MOSFET having a source-drain path which is supplied with the readout current from the selected memory cell and having a gate which is supplied with the comparison input information.
Claim 2
Dependent Claim
163 words
A semiconductor memory device, comprising: a plurality of memory cells for storing information; and a plurality of comparator circuits each of which being coupled for respectively comparing units of information stored in ones of said plurality of memory cells with comparison input information, corresponding to each unit of the information, and outputting a result of each comparison, wherein readout currents from ones of said plurality of memory cells being read out are respectively supplied to corresponding ones of said plurality of comparator circuits without first being converted into a voltage, wherein each one of said plurality of comparator circuits provides a comparison operation of readout current from a selected one of corresponding ones of said plurality of memory cells with comparison input information supplied thereto, and wherein each of the comparator circuits includes a MOSFET having a source-drain path which is supplied with the readout current from the selected memory cell and having a gate which is supplied with the comparison input information.
Claim 3
Dependent Claim
164 words
A semiconductor memory device, comprising: a plurality of memory cells for storing information; and a plurality of comparator circuits each of which being coupled for respectively comparing units of information stored in ones of said plurality of memory cells with comparison input information, corresponding to each unit of the information, and outputting a result of each comparison, wherein readout currents from ones of said plurality of memory cells being read out are respectively supplied to corresponding ones of said plurality of comparator circuits without first being converted into a voltage, wherein each one of said plurality of comparator circuits provides a comparison operation of readout current from a selected one of corresponding ones of said plurality of memory cells with comparison input information supplied thereto, and wherein each of the comparator circuits includes a bipolar transistor having an emitter-collector path which is supplied with the readout current from the selected memory cell and having a base which is supplied with the comparison input information.
Claim 4
Dependent Claim
164 words
A semiconductor memory device, comprising: a plurality of memory cells for storing information; and a plurality of comparator circuits each of which being coupled for respectively comparing units of information stored in ones of said plurality of memory cells with comparison input information, corresponding to each unit of the information, and outputting a result of each comparison, wherein readout currents from ones of said plurality of memory cells being read out are respectively supplied to corresponding ones of said plurality of comparator circuits without first being converted into a voltage, wherein each one of said plurality of comparator circuits provides a comparison operation of readout current from a selected one of corresponding ones of said plurality of memory cells with comparison input information supplied thereto, and wherein each of the comparator circuits includes a bipolar transistor having an emitter-collector path which is supplied with the readout current from the selected memory cell and having a base which is supplied with the comparison input information.
Claim 5
Dependent Claim
55 words
A semiconductor memory device according to claim 1, wherein outputs of said plurality of comparator circuits are connected with a matching detection line which effects a wired logic function, and wherein a matching detection signal is outputted to said matching detection line in accordance with the respective comparison results of said plurality of comparator circuits.
Claim 6
Dependent Claim
28 words
A semiconductor memory device according to claim 3, wherein said matching detection signal outputted to said matching detection line includes the readout current of the selected memory cell.
Claim 7
Dependent Claim
28 words
A semiconductor memory device according to claim 4, wherein said matching detection line is connected to a sensing circuit from which a matching detection voltage signal is generated.
Claim 8
Dependent Claim
57 words
A semiconductor memory device according to claim 3, further including a plurality of output circuits respectively provided for said plurality of comparison circuits, wherein each output circuit is coupled to a respective comparison circuit and comprises an emitter follower circuit, the emitter of said emitter follower circuit is an output thereof connected with said matching detection line.
Claim 9
Dependent Claim
176 words
A semiconductor memory device, comprising: a first memory array including a plurality of memory cells for storing information; a second memory array including a plurality of memory cells for storing information; and a matching detection circuit for comparing information stored in one of said plurality of memory cells selected from said first memory cell array with information stored in one of said plurality of memory cells selected from said second memory cell array and for outputting a matching detection signal based on a result of the comparison, wherein a readout signal from the selected memory cell from said first memory cell array and a readout signal from the selected memory cell from said second memory cell array are supplied to said matching detection circuit without requiring amplification of voltage signal representations thereof, and wherein said matching detection circuit includes an integrally arranged sensing and matching detection circuit for sensing the readout signal from the selected memory cells and thereafter carrying out a matching detection by said sensing and matching detection circuit based on the sensing result.
Claim 10
Dependent Claim
176 words
A semiconductor memory device, comprising: a first memory array including a plurality of memory cells for storing information; a second memory array including a plurality of memory cells for storing information; and a matching detection circuit for comparing information stored in one of said plurality of memory cells selected from said first memory cell array with information stored in one of said plurality of memory cells selected from said second memory cell array and for outputting a matching detection signal based on a result of the comparison, wherein a readout signal from the selected memory cell from said first memory cell array and a readout signal from the selected memory cell from said second memory cell array are supplied to said matching detection circuit without requiring amplification of voltage signal representations thereof, and wherein said matching detection circuit includes an integrally arranged sensing and matching detection circuit for sensing the readout signal from the selected memory cells and thereafter carrying out a matching detection by said sensing and matching detection circuit based on the sensing result.
Claim 11
Dependent Claim
79 words
A semiconductor memory device according to claim 7, wherein said sensing and matching detection circuit which integrally performs the sensing and matching detection operations includes at least ECL transistors, one of said ECL transistors having a base which is supplied with the readout signal from a first one of the selected memory cells and each of said ECL transistors having a collector-emitter path which performs a switching function associated with a differential current to carry out the matching detection.
Claim 12
Dependent Claim
27 words
A semiconductor memory device according to claim 8, wherein the differential current includes the readout current from the selected memory cell from said second memory cell array.
Claim 13
Dependent Claim
131 words
A semiconductor memory device according to claim 7, wherein the readout current from the selected memory cell from said first memory cell array, corresponding to said first one of the selected memory cells, and the readout current from the selected memory cell from the second memory cell array are applied to the sensing and matching detection circuit, the applied readout currents are sensed by the sensing and matching detection circuit, and wherein the sensing and matching detection circuit has a plurality of resistors for converting a plurality of matching detection currents based on the sensing result into voltages and a plurality of bipolar transistors, each base of which is supplied with the voltage from each of the resistors, and each emitter of which is connected with a matching detection signal line.
Claim 14
Dependent Claim
47 words
A semiconductor memory device according to claim 7, wherein the first memory cell array includes a memory array for storing physical address of an address translation cache, and wherein the second memory cell array includes a tag array for storing address of an instruction or data cache.
Claim 15
Dependent Claim
19 words
A semiconductor memory device according to claim 6, wherein said matching detection line performs a wired AND logic operation.
Claim 16
Dependent Claim
26 words
A semiconductor memory device according to claim 12, wherein each one of said plurality of comparator circuits includes means for performing an exclusive NOR logic operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-10-11 | 1997-04-12 | 1997-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-11 | 2001-04-12 | 2001-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-11 | 2005-04-12 | 2005-10-12 | $7700.00 | Window Closed / Lapsed |