US4866673A
Expired / Lapsed
US
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BI-MOS semiconductor memory having high soft error immunity
Assignee: Hitachi Ltd
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Filing: 1987-04-16
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Granted: 1989-09-12
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Expires: 2007-04-16
Abstract
Abstract A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by alpha rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage VD and the word line voltage VW satisfy the relation VW<VD+VTH in a read cycle and the relation VW>VD+VTH in a write cycle (where VTH is the threshold voltage of NMOS inside the memory cell).
Inventors
- 👤 Hisayuki Higuchi
- 👤 Makoto Suzuki
- 👤 Noriyuki Homma
- 👤 Kiyoo Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:14
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418; G11C11/419
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
162 words
A semiconductor memory comprising: a plurality of pairs of data lines; a plurality of word lines orthogonally crossing said data lines; and a detection circuit for detecting memory data from a conduction ratio between a transistor of a flip-flop type memory cell, which is connected to one of said word lines and one pair of said plurality of pairs of data lines, and a load device which is connected to one data line of said one pair of said data lines, wherein the voltage of said word line for reading out said memory data from said flip-flop type memory cell is set to a voltage lower than the sum of the voltage of said data line and the threshold voltage of a data transfer MOS transistor of said memory cell, and a signal read out from said memory cell through said data line is inputted to a differential amplifier using a base or gate of a junction type transistor as its input.
Claim 2
Dependent Claim
162 words
A semiconductor memory comprising: a plurality of pairs of data lines; a plurality of word lines orthogonally crossing said data lines; and a detection circuit for detecting memory data from a conduction ratio between a transistor of a flip-flop type memory cell, which is connected to one of said word lines and one pair of said plurality of pairs of data lines, and a load device which is connected to one data line of said one pair of said data lines, wherein the voltage of said word line for reading out said memory data from said flip-flop type memory cell is set to a voltage lower than the sum of the voltage of said data line and the threshold voltage of a data transfer MOS transistor of said memory cell, and a signal read out from said memory cell through said data line is inputted to a differential amplifier using a base or gate of a junction type transistor as its input.
Claim 3
Dependent Claim
126 words
A semiconductor memory according to claim 1, wherein in order to set said word line voltage to a voltage lower than the sum of said data line voltage and the threshold voltage of said data transfer MOS transistor of said memory cell, a device having high driving capability is used as the load of said data line, and wherein said word line voltage is changed over to two stages so that the relationship between said data line voltage V D and said word line voltage V W satisfy the relation V W <V D +V TH in the read cycle and the relation V W >V D +V TH in the write cycle (where V TH is the threshold value of NMOS inside said memory cell).
Claim 4
Dependent Claim
44 words
A semiconductor memory according to claim 1, further comprising first common data lines disposed in common for a plurality of said data lines, wherein an emitter or source (drain) of said junction type transistor is connected to each of said first common data line.
Claim 5
Dependent Claim
42 words
A semiconductor memory according to claim 3, wherein said data lines and said word lines constitute a plurality of memory arrays, and said first common data lines are connected in common to said data lines existing inside one of said memory arrays.
Claim 6
Dependent Claim
34 words
A semiconductor memory according to claim 4, further comprising second common data lines disposed in common on said first common data lines, wherein memory data are read out from said second common data lines.
Claim 7
Dependent Claim
184 words
A semiconductor memory comprising: a plurality of pairs of data lines; a plurality of word lines orthogonally crossing said data lines; word drivers for driving said word lines; and a detection circuit for detecting memory data from a conduction ratio between a transistor of a flip-flop type memory cell, which is connected to one of said word lines and one pair of said plurality of pairs of data lines, and a load device which is connected to one data line of said one pair of said data lines, wherein the voltage of said word line for reading out said memory data from said flip-flop type memory cell is set to a voltage lower than the sum of the voltage of said data line and the threshold voltage of a data transfer MOS transistor of said memory cell, wherein a switch circuit is disposed on said data line pair to share a differential amplifier by an ON/OFF operation of said switch circuit, and wherein emitters of a plurality of level-shifting emitter followers are connected in parallel with one another and led to said differential amplifier.
Claim 8
Dependent Claim
184 words
A semiconductor memory comprising: a plurality of pairs of data lines; a plurality of word lines orthogonally crossing said data lines; word drivers for driving said word lines; and a detection circuit for detecting memory data from a conduction ratio between a transistor of a flip-flop type memory cell, which is connected to one of said word lines and one pair of said plurality of pairs of data lines, and a load device which is connected to one data line of said one pair of said data lines, wherein the voltage of said word line for reading out said memory data from said flip-flop type memory cell is set to a voltage lower than the sum of the voltage of said data line and the threshold voltage of a data transfer MOS transistor of said memory cell, wherein a switch circuit is disposed on said data line pair to share a differential amplifier by an ON/OFF operation of said switch circuit, and wherein emitters of a plurality of level-shifting emitter followers are connected in parallel with one another and led to said differential amplifier.
Claim 9
Dependent Claim
123 words
A semiconductor memory according to claim 6, wherein in order to set said word line voltage to a voltage lower than the sum of said data line voltage and the threshold voltage of said data transfer MOS transistor of said memory cell, a device having high driving capability is used as the load of said data line, and wherein said word line voltage is changed over to two stages so that said data line voltage V D and said word line voltage V W satisfy the relation V W <V D +V TH in the read cycle and the relation V W >V D +V TH in the write cycle (where V TH is the threshold value of NMOS inside said memory cell).
Claim 10
Dependent Claim
44 words
A semiconductor memory according to claim 6, further comprising first common data lines disposed in common for a plurality of said data lines, wherein an emitter or source (drain) of said junction type transistor is connected to each of said first common data line.
Claim 11
Dependent Claim
42 words
A semiconductor memory according to claim 8, wherein said data lines and said word lines constitute a plurality of memory arrays, and said first common data lines are connected in common to said data lines existing inside one of said memory arrays.
Claim 12
Dependent Claim
34 words
A semiconductor memory according to claim 9, further comprising second common data lines disposed in common on said first common data lines, wherein memory data are read out from said second common data lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-11 | 1993-03-13 | 1993-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-11 | 1997-03-13 | 1997-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-11 | 2001-03-13 | 2001-09-12 | $7700.00 | Window Closed / Lapsed |