High speed CMOS output buffer circuit minimizes output signal oscillation and steady state current

Claim 2

A high speed output buffer circuit for minimizing output signal oscillation and steady state current comprising: first and second drive transistors, a pair of reference voltage generators, one of the pair of voltage generators coupled to the first drive transistor, the other of the pair of voltage generators being coupled to the second drive transistor, one of the pair of voltage generators including primarily p-type transistors, the other of the pair of the voltage generators including primarily n-type transistors, each of the reference voltage generators being coupled in a current mirror configuration, means responsive to the pair of voltage generators for providing a controlled ramping of the output voltage of at least one of the drive transistors to minimize steady state current output signal oscillation; and means coupled to the pair of voltage generators for shutting down the pair of reference generator when the output oscillation has subsided to some acceptable level.

Claim 3

The high speed output buffer circuit of claim 1 in which each of the reference generators comprises: a plurality of transistors connected in series and ratioed such that each of the plurality of transistors has a threshold voltage that is a level higher than the preceding one, and a load transistor coupled to the plurality of series transistors.

Claim 4

The output buffer circuit of claim 1 in which a first reference voltage generator provides a clamp voltage which is two threshold voltages above V ss and a second reference voltage generator provides a clamp voltage which is two threshold voltages below V cc .

Claim 5

The output buffer circuit of claim 1 in which the first reference generator provides a clamp voltage which is three threshold voltages above V ss and a second reference voltage generator in which the clamp voltage is three threshold voltages below V cc .

Claim 6

The output buffer circuit of claim 1 in which the first reference voltage generator provides a clamp voltage which is four threshold voltages above V ss and a second reference voltage generator which is four threshold voltages below V cc .

Claim 7

The output buffer circuit of claim 2 in which in each of the reference voltage generators, the plurality of series transistors are driven to saturation and the load transistor is weakly turned on.

Claim 8

The output buffer circuit of claim 2 in which the providing means comprises a means for shorting one of the series transistors in one of the reference voltage generators to change the clamp voltage when an input to the reference voltage generator is active.

Claim 9

The output buffer circuit of claim 2 in which the shutting down means comprises: means for driving the first and second driver transistors to their full CMOS voltage levels after the output signal oscillation has subsided to an acceptable level.

Claim 10

A high speed output buffer circuit for minimizing output signal oscillation and steady state current comprising; a nmos driver transistor, a pmos driver transistor, a first reference voltage generator coupled to the nmos driver transistor, the first reference voltage generator including primarily a plurality of nmos transistors, the plurality of nmos transistors being connected in a series fashion and in a circuit mirror configuration, the plurality of transistors being connected such that each of the transistors is at a threshold higher than the immediately preceding transistor, a second reference voltage generator coupled to the pmos driver transistor, the second reference voltage generator including primarily a plurality pmos transistors, the plurality of pmos transistors being connected in a series fashion and in a current mirror configuration, the plurality of transistors being connected such that each of the transistors is at a threshold voltage lower than the preceding transistor, and means reponsive to the first and second voltage generators for shutting down the appropriate reference voltage generator when the output oscillation has subsided to an acceptable level.

Claim 11

A high speed output buffer circuit for minimizing output signal oscillation and steady state current comprising; a nmos driver transistor, a pmos driver transistor, a first reference voltage generator coupled to the nmos driver transistor, the first reference voltage generator including primarily a plurality of nmos transistors, the plurality of nmos transistors being connected in a series fashion and in a circuit mirror configuration, the plurality of transistors being connected such that each of the transistors is at a threshold higher than the immediately preceding transistor, a second reference voltage generator coupled to the pmos driver transistor, the second reference voltage generator including primarily a plurality pmos transistors, the plurality of pmos transistors being connected in a series fashion and in a current mirror configuration, the plurality of transistors being connected such that each of the transistors is at a threshold voltage lower than the preceding transistor, and means reponsive to the first and second voltage generators for shutting down the appropriate reference voltage generator when the output oscillation has subsided to an acceptable level.

Claim 12

A high speed output buffer circuit for minimizing output signal oscillation and steady state current comprising: first and second drive transistors, a pair of reference voltage generators, one of the pair of voltage generators coupled to the first drive transistor, the other of the pair of voltage generators being coupled to the second drive transistor, one of the pair of voltage generators including primarily p-type transistors, the other of the pair of the voltage generators including primarily n-type transistors, each of the reference voltage generators being coupled in a current mirror configuration, and means responsive to the pair of voltage generators for providing a controlled ramping of the output voltage of at least one of the drive transistors to minimize steady state current output signal oscillation.

Claim 13

A high speed output buffer circuit for minimizing output signal oscillation and steady state current comprising: first and second drive transistors, a pair of reference voltage generators, one of the pair of voltage generators coupled to the first drive transistor, the other of the pair of voltage generators being coupled to the second drive transistor, one of the pair of voltage generators including primarily p-type transistors, the other of the pair of the voltage generators including primarily n-type transistors, each of the reference voltage generators being coupled in a current mirror configuration, and means responsive to the pair of voltage generators for providing a controlled ramping of the output voltage of at least one of the drive transistors to minimize steady state current output signal oscillation.

Claim 14

A high speed output buffer circuit for minimizing output signal oscillation and steady state current comprising: first and second drive transistors, a pair of reference voltage generators, one of the pair of voltage generators coupled to the first drive transistor, the other of the pair of voltage generators being coupled to the second drive transistor, one of the pair of voltage generators including primarily p-type transistors, the other of the pair of the voltage generators including primarily n-type transistors, each of the reference voltage generators being coupled in a current mirror configuration, and means coupled to the pair of voltage generators for shutting down the pair of reference generators when the output oscillation has subsided to some acceptable level.

Claim 15

A high speed output buffer circuit for minimizing output signal oscillation and steady state current comprising: first and second drive transistors, a pair of reference voltage generators, one of the pair of voltage generators coupled to the first drive transistor, the other of the pair of voltage generators being coupled to the second drive transistor, one of the pair of voltage generators including primarily p-type transistors, the other of the pair of the voltage generators including primarily n-type transistors, each of the reference voltage generators being coupled in a current mirror configuration, and means coupled to the pair of voltage generators for shutting down the pair of reference generators when the output oscillation has subsided to some acceptable level.