Apparatus for increasing the speed of operation of non-volatile memory arrays

Claim 1

An improvement in a memory array, the memory array including a first plurality of bitlines, a second plurality of memory devices, each memory device being connected to one bitline of the plurality of bitlines, each memory device having a first state in which current is transferred and a second state in which current is not transferred, a column select device for selectively activating a selected bitline of the plurality of the bitlines, a third plurality of wordlines for activating a selected memory device of the second plurality of memory devices, the third plurality of wordlines forming rows within the memory array, an entire row being activated when the selected memory device is activated, the selected memory device being connected to the selected bitline, means for providing a first constant current to the selected memory device, means for connecting a source voltage to the first plurality of bitlines, and a first reference bitline for providing an output reference signal, the improvement comprising: a) a first means for providing a second current to the selected memory device to accelerate switching to the selected memory device, the means for providing a second current including: 1) a second reference bitline to charge any capacitance of the selected bitline when the selected bitline is selected; and 2) a second means for joining the second reference bitline to the selected bitline when the selected bitline is selected and for disconnecting the second reference bitline from the selected bitline before the selected memory device is sensed.