US5063540A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory circuit with diode load circuits
Assignee: NEC Corp
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Filing: 1991-02-08
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Granted: 1991-11-05
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Expires: 2011-02-08
Abstract
Abstract A semiconductor memory circuit comprises memory cells, word lines, digit line pairs, load elements, a data bus line pair and a sense amplifier. The load elements are diode type semiconductor elements, and the information of the memory cell is read by using potential difference in forward voltages of the elements.
Inventors
- 👤 Hiroyuki Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:22
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
103 words
A semiconductor memory circuit transmitting information in a memory cell connected to a selected word line and a selected digit line pair to a sense amplifier through a data bus line pair, wherein the information of said memory cell is read by sensing a potential difference generated at load diodes by supplying a cell current through either of said digit line pair in accordance with memory data of said memory cell, said load diodes being respectively connected to said digit line pair or data bus line pair as load elements to supply the information stored in said memory cell to said sense amplifier.
Claim 2
Dependent Claim
103 words
A semiconductor memory circuit transmitting information in a memory cell connected to a selected word line and a selected digit line pair to a sense amplifier through a data bus line pair, wherein the information of said memory cell is read by sensing a potential difference generated at load diodes by supplying a cell current through either of said digit line pair in accordance with memory data of said memory cell, said load diodes being respectively connected to said digit line pair or data bus line pair as load elements to supply the information stored in said memory cell to said sense amplifier.
Claim 3
Dependent Claim
40 words
A semiconductor memory circuit as claimed in claim 1, wherein a constant current circuit which simulates the memory cell is further provided so as to let a minute current as an offset current flow in both said diode devices, constantly.
Claim 4
Dependent Claim
98 words
A semiconductor memory circuit as claimed in claim 1, in which said diode devices are bipolar transistors, said bipolar transistors are used to execute the operation of lowering the potential of either one of a selected digit line pair to the vicinity of a lowest potential and the operation of recovering the potential to the original value after the completion of writing either directly by means of said digit line pair or via a data bus line that collected information of a plurality of digit line pairs in order to write a data to a selected memory cell.
Claim 5
Dependent Claim
86 words
A semiconductor memory circuit comprising: a memory cell arranged at the intersection of a digit line pair and a word line; a switching circuit connected to said digit line pair; a load circuit having PN-junction diode connected to said switching circuit via a bus; a constant current source circuit for supplying an offset current that flows in the diode of said load circuit; and a sense amplifier connected to said load circuit and amplifies the potential difference generated by the current that flows in said diode.
Claim 6
Dependent Claim
86 words
A semiconductor memory circuit comprising: a memory cell arranged at the intersection of a digit line pair and a word line; a switching circuit connected to said digit line pair; a load circuit having PN-junction diode connected to said switching circuit via a bus; a constant current source circuit for supplying an offset current that flows in the diode of said load circuit; and a sense amplifier connected to said load circuit and amplifies the potential difference generated by the current that flows in said diode.
References Cited (Backward Citations)
US4829479A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-04 | 1995-05-06 | 1995-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-04 | 1999-05-06 | 1999-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-04 | 2003-05-06 | 2003-11-05 | $7700.00 | Window Closed / Lapsed |