Integrated circuit

Claim 2

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said gate electrode is made of carbide.

Claim 3

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said semiconductor is p conductivity type silicon and said gate electrode is LaB 6 .

Claim 4

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said semiconductor is p conductivity type silicon and said gate electrode is LaB 6 .

Claim 5

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said semiconductor is p conductivity type silicon and said gate electrode is Zrn.

Claim 6

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said semiconductor is p conductivity type silicon and said gate electrode is Zrn.

Claim 7

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said semiconductor is p conductivity type silicon and said gate electrode is Tan.

Claim 8

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said semiconductor is p conductivity type silicon and said gate electrode is Tan.

Claim 9

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said semiconductor is p conductivity type silicon and said gate electrode is ZrC.

Claim 10

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed in the neighborhood of said source region on the principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate between said source region and said drain region, which portion is not doped with n conductivity type impurities; and a gate electrode formed on said gate insulating film having a work function smaller than that of said p conductivity type semiconductor substrate; wherein said semiconductor is p conductivity type silicon and said gate electrode is ZrC.

Claim 11

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed near said source region on said principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate which is between said source region and said drain region and which is not doped with n conductivity type impurities; and a gate electrode which is formed on said gate insulating film and has a work function smaller than about 4 eV; wherein said surface portion of said semiconductor substrate between said source region and said drain region, which is not doped with n conductivity type impurities, is doped with impurities of the same conductivity type as said semiconductor substrate and at a density greater than that of said semiconductor substrate; wherein a distance as an effective channel length between said source region and said drain region formed on said surface of said semiconductor substrate is smaller than 0.5 μm; wherein said source and drain regions are portions of a depletion type field effect transistor; and wherein one of a source-drain voltage for said depletion type field effect transistor, a voltage between a ground of an enhancement/depletion type inverter and the drain of said depletion type field effect transistor, and a voltage supplied to said semiconductor integrated circuit is below 5 V DC.

Claim 12

An integrated circuit including depletion type field effect transistors, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed near said source region on said principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate which is between said source region and said drain region and which is not doped with n conductivity type impurities; and a gate electrode which is formed on said gate insulating film and has a work function smaller than about 4 eV; wherein said surface portion of said semiconductor substrate between said source region and said drain region, which is not doped with n conductivity type impurities, is doped with impurities of the same conductivity type as said semiconductor substrate and at a density greater than that of said semiconductor substrate; wherein a distance as an effective channel length between said source region and said drain region formed on said surface of said semiconductor substrate is smaller than 0.5 μm; wherein said source and drain regions are portions of a depletion type field effect transistor; and wherein one of a source-drain voltage for said depletion type field effect transistor, a voltage between a ground of an enhancement/depletion type inverter and the drain of said depletion type field effect transistor, and a voltage supplied to said semiconductor integrated circuit is below 5 V DC.

Claim 13

An integrated circuit according to claim 6, wherein said gate electrode is LaB 6 .

Claim 14

An integrated circuit according to claim 6, wherein said gate electrode is TiN.

Claim 15

An integrated circuit according to claim 6, wherein a working temperature of said integrated circuit is below 90K.

Claim 16

An integrated circuit according to claim 9, wherein said gate electrode is TiN.

Claim 17

An integrated circuit according to claim 6, wherein said gate electrode is made of a nitride.

Claim 18

An integrated circuit according to claim 11, wherein said nitride is ZrN.

Claim 19

An integrated circuit according to claim 11, wherein said nitride is TaN.

Claim 20

An integrated circuit according to claim 6, wherein said gate electrode is made of a carbide.

Claim 21

An integrated circuit according to claim 14, wherein said carbide is ZrC.

Claim 22

An integrated circuit including depletion type field effect transistors, comprising: an n conductivity type semiconductor substrate having a principal surface side; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed near said source region on said principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate which is between said source region and said drain region and which is not doped with p conductivity type impurities; and a gate electrode which is formed on said gate insulating film and has a work function greater than about 5.5 eV; wherein said surface portion of said semiconductor substrate between said source region and said drain region, which is not doped with p conductivity type impurities, is doped with impurities of the same conductivity type as said semiconductor substrate and at a density greater than that of said semiconductor substrate; wherein a distance as an effective channel length between said source region and said drain region formed on said surface of said semiconductor substrate is smaller than 0.5 μm; wherein said source and drain regions are portions of a depletion type field effect transistor; and wherein one of a source-drain voltage for said depletion type field effect transistor, a voltage between a ground of an enhancement/depletion type inverter and the drain of said depletion type field effect transistor, and a voltage supplied to said semiconductor integrated circuit is below 5 V DC.

Claim 23

An integrated circuit including depletion type field effect transistors, comprising: an n conductivity type semiconductor substrate having a principal surface side; a source region formed on the principal surface side of said semiconductor substrate; a drain region formed near said source region on said principal surface side of said semiconductor substrate; a gate insulating film formed on the surface portion of said semiconductor substrate which is between said source region and said drain region and which is not doped with p conductivity type impurities; and a gate electrode which is formed on said gate insulating film and has a work function greater than about 5.5 eV; wherein said surface portion of said semiconductor substrate between said source region and said drain region, which is not doped with p conductivity type impurities, is doped with impurities of the same conductivity type as said semiconductor substrate and at a density greater than that of said semiconductor substrate; wherein a distance as an effective channel length between said source region and said drain region formed on said surface of said semiconductor substrate is smaller than 0.5 μm; wherein said source and drain regions are portions of a depletion type field effect transistor; and wherein one of a source-drain voltage for said depletion type field effect transistor, a voltage between a ground of an enhancement/depletion type inverter and the drain of said depletion type field effect transistor, and a voltage supplied to said semiconductor integrated circuit is below 5 V DC.

Claim 24

An integrated circuit according to claim 16, wherein said gate electrode is Pt.

Claim 25

An integrated circuit according to claim 16, wherein a working temperature of said integrated circuit is below 90K.

Claim 26

An integrated circuit according to claim 18, wherein said gate electrode is Pt.

Claim 27

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p or n conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET has a work function which is respectively smaller than about 4 eV and greater than about 5.5 eV when said semiconductor substrate is respectively of p conductivity type and n conductivity type; wherein said surface portion of said semiconductor substrate between said source region and said drain region of said depletion type MOSFET, which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate, is doped with impurities of the same conductivity type as said semiconductor substrate and at a density greater than that of said semiconductor substrate; and wherein one of a source-drain voltage for said depletion type field effect transistor, a voltage between a ground of said enhancement/depletion type inverter and said drain of said depletion type field effect transistor, and a voltage supplied to said semiconductor integrated circuit is below 5 V DC.

Claim 28

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p or n conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET has a work function which is respectively smaller than about 4 eV and greater than about 5.5 eV when said semiconductor substrate is respectively of p conductivity type and n conductivity type; wherein said surface portion of said semiconductor substrate between said source region and said drain region of said depletion type MOSFET, which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate, is doped with impurities of the same conductivity type as said semiconductor substrate and at a density greater than that of said semiconductor substrate; and wherein one of a source-drain voltage for said depletion type field effect transistor, a voltage between a ground of said enhancement/depletion type inverter and said drain of said depletion type field effect transistor, and a voltage supplied to said semiconductor integrated circuit is below 5 V DC.

Claim 29

An integrated circuit according to claim 20, wherein said semiconductor substrate is p conductivity type silicon and said gate electrode for said depletion type MOSFET is TiN.

Claim 30

An integrated circuit according to claim 20, wherein said semiconductor substrate is n conductivity type silicon and said gate electrode for said depletion type MOSFET is Pt.

Claim 31

An integrated circuit according to claim 20, wherein said gate electrode for said depletion type MOSFET is made of a carbide.

Claim 32

An integrated circuit according to claim 20, wherein a working temperature of said integrated circuit is below about 90K.

Claim 33

An integrated circuit according to claim 24, wherein said semiconductor substrate is p conductivity type silicon and said gate electrode for said depletion type MOSFET is TiN.

Claim 34

An integrated circuit according to claim 24, wherein said semiconductor substrate is n conductivity type silicon and said gate electrode for said depletion type MOSFET is Pt.

Claim 35

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of carbide, and has a work function which is smaller than about 4 eV.

Claim 36

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of carbide, and has a work function which is smaller than about 4 eV.

Claim 37

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of LaB 6 , and has a work function which is smaller than about 4 eV.

Claim 38

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of LaB 6 , and has a work function which is smaller than about 4 eV.

Claim 39

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of ZrN, and has a work function which is smaller than about 4 eV.

Claim 40

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of ZrN, and has a work function which is smaller than about 4 eV.

Claim 41

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of TaN, and has a work function which is smaller than about 4 eV.

Claim 42

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of TaN, and has a work function which is smaller than about 4 eV.

Claim 43

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of ZrC, and has a work function which is smaller than about 4 eV.

Claim 44

An integrated circuit including at least one enhancement/depletion inverter, comprising: a p conductivity type semiconductor substrate having a principal surface side; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET formed at spaced locations on said principal surface side of said semiconductor substrate; an island-shaped common region which acts as a drain region of said enhancement type MOSFET and as a source region of said depletion type MOSFET and which is formed on said principal surface side of said substrate between source region of said enhancement type MOSFET and said drain region of said depletion type MOSFET; a gate insulating film for said depletion type MOSFET formed on a surface portion of said semiconductor substrate which is between said drain region of said depletion type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; a gate electrode for said depletion type MOSFET formed on said gate insulating film for said depletion type MOSFET: an electrode formed on said common region and connected electrically with said gate electrode for said depletion type MOSFET; a gate insulating film for said enhancement type MOSFET formed on a surface portion of said semiconductor substrate which is between said source region of said enhancement type MOSFET and said common region and which is not doped with impurities of a conductivity type opposite to the conductivity type of said semiconductor substrate; and a gate electrode for said enhancement type MOSFET formed on said gate insulating film for said enhancement type MOSFET: wherein said gate electrode for said depletion type MOSFET is made of ZrC, and has a work function which is smaller than about 4 eV.