Instruction handling sequence control system for simultaneous execution of instructions

Claim 1

A computer program instruction sequence control system to allow parallel execution of instructions comprising: (a) an instruction storage section containing at least a first instruction and a second instruction for sequence determination; (b) a main storage referencing logic contention connecting section to determine if said first instruction and said second instruction reference a same address, and for judging an overlapping relationship between a load starting point address of a vector load instruction and a vector store instruction; (c) a register referencing logic contention checking section to determine if said first instruction writes into or reads from said second instruction, and if said second instruction writes into or reads from said first instruction; (d) a state holding section to determine if said first instruction or said second instruction contends for a plurality of registers, an arithmetic unit, or a main storage handling used by an instruction currently under execution; and (e) an instruction issue deciding section which receives information from said main storage referencing logic connecting section, said register referencing logic contention checking section, and said state holding section and allows parallel execution of said first and said second instructions following a determination that no instruction interference occurs and that there is no logical sequential relationship between said first and said second instructions.