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US5239481A
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Method for measuring pulse distortion
Assignee: International Business Machines Corp
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Filing: 1991-08-30
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Granted: 1993-08-24
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Expires: 2011-08-30
Abstract
Abstract A method for measuring pulse distortion in a digital logic design. A digital logic block of interest is divided into its component primary logic functions. The pulse width distortion characteristics are determined for each primary logic function. The pulse width distortion characteristics are used to develop values representing the minimum pulse width required to guarantee full pulse amplitude propagation through each primary logic function. Thus, pulse distortion is characterized in terms of both width and amplitude components. Pulse width distortion for the entire logic block is then determined by following each logic path through the logic block and statistically summing the pulse width distortion characteristics for each occurrence of each primary logic function in the logic path. Pulse amplitude integrity is checked at the input to each primary logic function by referencing the pre-calculated values for minimum pulse width required to guarantee full pulse amplitude propagation through the primary logic function.
Inventors
- 👤 Thomas W. Brooks
- 👤 Paul T. Gutwin
- 👤 Caryn G. Melrose
- 👤 Frank A. Nemec, Jr.
- 👤 James J. Tomczak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:33
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
148 words
A method for determining pulse distortion in a simulated logic block of a simulated electronic circuit design, comprising the steps of: segmenting the simulated logic block into simulated primary logic functions; determining a simulated pulse distortion described by pulse width, pulse amplitude, and pulse polarity for each of the simulated primary logic functions based on design parameters for the simulated primary logic functions by applying a simulated sample pulse described by a pulse width, pulse amplitude, and pulse polarity to each of the simulated primary logic functions for the design parameters; storing the determined distortion characteristic in computer memory; and determining cumulative distortion for each logic path through the simulated logic block by statistically summing the stored distortion characteristics for each of the simulated primary logic functions along the logic path, the statistical summation including a correlation coefficient which compensates for interactions between the simulated primary logic functions.
Claim 2
Independent Claim
148 words
A method for determining pulse distortion in a simulated logic block of a simulated electronic circuit design, comprising the steps of: segmenting the simulated logic block into simulated primary logic functions; determining a simulated pulse distortion described by pulse width, pulse amplitude, and pulse polarity for each of the simulated primary logic functions based on design parameters for the simulated primary logic functions by applying a simulated sample pulse described by a pulse width, pulse amplitude, and pulse polarity to each of the simulated primary logic functions for the design parameters; storing the determined distortion characteristic in computer memory; and determining cumulative distortion for each logic path through the simulated logic block by statistically summing the stored distortion characteristics for each of the simulated primary logic functions along the logic path, the statistical summation including a correlation coefficient which compensates for interactions between the simulated primary logic functions.
Claim 3
Dependent Claim
47 words
A method for measuring pulse distortion as recited in claim 1, wherein the simulated pulse distortion for each of the simulated primary logic functions is determined by providing values for design parameters to a circuit simulation tool to generate a pulse distortion value for the design parameters.
Claim 4
Dependent Claim
66 words
A method for measuring pulse distortion as recited in claim 2, wherein the statistical summing of the stored distortion characteristics includes compensating for interactions between the simulated primary logic functions in accordance with the correlation coefficients, and summing the compensated individual pulse distortion characteristics for each of the simulated primary logic functions along a logic path to determine a cumulative pulse distortion for the logic path.
Claim 5
Dependent Claim
51 words
A method for measuring pulse distortion as recited in claim 3, further comprising the step of: determining for each of the simulated primary logic functions and the design parameters, based on the simulated pulse distortion and the associated design parameters, a minimum pulse width value required to maintain pulse amplitude integrity.
Claim 6
Dependent Claim
147 words
A method for measuring pulse distortion as recited in claim 4, further comprising the steps of: applying a simulated design pulse to each logic path of the simulated logic block; for each occurrence of each of the simulated primary logic functions through the logic path from input to output, determining the propagated state of the simulated design pulse through the simulated primary logic function by statistically summing the pulse distortion characteristics of the simulated primary logic function with the propagated state of the simulated design pulse at an input of the simulated primary logic function, and determining pulse amplitude integrity of the simulated design pulse at an output of the simulated primary logic function by comparing the propagated state of the simulated design pulse at the input to the simulated primary logic function occurrence with the associated minimum pulse width value required to maintain pulse amplitude integrity.
Claim 7
Independent Claim
158 words
A method for measuring pulse distortion in a simulated logic block of a simulated electronic circuit design, comprising the steps of: assigning statistical distributions for circuit process parameters associated with the simulated electronic circuit design; segmenting the simulated logic block into simulated primary logic functions; determining simulated pulse width distortion and pulse amplitude distortion characteristics of each simulated primary logic function for positive and negative pulse polarity based on the assigned statistical distributions, selected design parameters for the simulated primary logic function, and selected environmental parameters by applying a sample pulse to the simulated primary logic function; storing the simulated pulse width and pulse amplitude distortion characteristics in computer memory; and determining cumulative distortion for each logic path through the simulated logic block by statistically summing the distortion characteristics for each of the simulated primary logic functions along the logic path, the statistical summation including a correlation coefficient which compensates for interactions between the simulated primary logic functions.
Claim 8
Independent Claim
158 words
A method for measuring pulse distortion in a simulated logic block of a simulated electronic circuit design, comprising the steps of: assigning statistical distributions for circuit process parameters associated with the simulated electronic circuit design; segmenting the simulated logic block into simulated primary logic functions; determining simulated pulse width distortion and pulse amplitude distortion characteristics of each simulated primary logic function for positive and negative pulse polarity based on the assigned statistical distributions, selected design parameters for the simulated primary logic function, and selected environmental parameters by applying a sample pulse to the simulated primary logic function; storing the simulated pulse width and pulse amplitude distortion characteristics in computer memory; and determining cumulative distortion for each logic path through the simulated logic block by statistically summing the distortion characteristics for each of the simulated primary logic functions along the logic path, the statistical summation including a correlation coefficient which compensates for interactions between the simulated primary logic functions.
Claim 9
Dependent Claim
53 words
A method for measuring pulse distortion as recited in claim 6, further including the step, prior to the first determining step, of: segmenting each of the simulated primary logic functions into combinations of input and output pins, and wherein the first determining step is repeated for each combination of input and output pins.
Claim 10
Dependent Claim
93 words
A method for measuring pulse distortion as recited in claim 7, wherein the pulse width and pulse amplitude distortion characteristics of each of the simulated primary logic functions are determined by applying values for the assigned statistical distributions, the selected design parameters, and the selected environmental parameters to a circuit simulation tool to generate a pulse width distortion value for the selected design parameters and environmental parameters; determining, as a function of each pulse width distortion value and the selected design parameters, a minimum pulse width value required to maintain pulse amplitude integrity.
Claim 11
Dependent Claim
51 words
A method for measuring pulse distortion as recited in claim 8, wherein the minimum pulse width value is determined by adding the pulse width distortion value to the time lapse between a specified point on a leading edge and a specified point on a trailing edge contiguous with the leading edge.
Claim 12
Dependent Claim
23 words
A method for measuring pulse distortion as recited in claim 9, wherein the selected design parameters include capacitive loading and input rise/fall times.
Claim 13
Dependent Claim
21 words
A method for measuring pulse distortion as recited in claim 10, wherein the selected environmental parameters include temperature and supply voltage.
Claim 14
Dependent Claim
25 words
A method for measuring pulse distortion as recited in claim 11, wherein the circuit process parameters include carrier mobility, effective channel length, and threshold voltage.
Claim 15
Dependent Claim
18 words
A method for measuring pulse distortion as recited in claim 12, wherein the statistical distributions are Gaussian distributions.
Claim 16
Dependent Claim
71 words
A method for measuring pulse distortion as recited in claim 6, wherein the statistical summation in the second determining step includes the substeps of: compensating for interactions between the simulated primary logic functions in accordance with the correlation coefficients; and summing the individual compensated pulse width distortion values for each of the simulated primary logic functions along the logic path to determine a cumulative pulse width distortion for the logic path.
Claim 17
Dependent Claim
30 words
A method for measuring pulse distortion as recited in claim 14, wherein the pulse width distortion values are mean values and the cumulative pulse width distortion is a mean value.
Claim 18
Dependent Claim
127 words
A method for measuring the pulse distortion as recited in claim 15, wherein the correlation coefficient relates the cumulative pulse width distortion for each of the simulated primary logic functions as determined by summing the individual pulse width distortion values for each of the simulated primary logic functions with the cumulative pulse width distortion for the coupled primary logic functions as determined by any of a circuit simulation tool and a circuit prototype, and wherein the statistical summation in the second determining step further includes the substep of summing standard deviation values for the individual pulse width distortion values, each adjusted in response to its corresponding correlation value, for each simulated circuit type along the logic path to determine a cumulative standard deviation for the logic path.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |