Digital signal processing system

Claim 2

In a method of signal processing a batch-bulk coded digital signal that is segmented into variable-length words which are allocated to constant-length blocks, a given constant-length block receiving a variable-length word which is shorter than a predetermined word length together with a portion of a variable-length word which is longer than said predetermined word length for filling up said given block, an improvement comprising the steps of: combining several successive constant-length blocks into a superblock which defines a portion of a picture; adding an address word to said superblock to identify the location of said superblock picture portion within said picture.

Claim 3

The method of claim 1 further including the step of temporarily storing said variable-length words in a storing medium and utilizing a level of filling of the storing medium to control a quantizer characteristic curve of a coding section.

Claim 4

The method of claim 2, wherein said superblock is decoded at a search speed in substantially equal temporal intervals, said address word locating said superblock at a location substantially the same as that decoded at normal reading speed.

Claim 5

A coder for a digital processing system of block, transform coded signals, said transform coded signals having coefficients representing dc components, more important alternating components, and less important alternating components, said coder comprising: quantizing and coding means for quantizing said block transform coded signals and for coding said signals into variable-length words; means coupled to said quantizing and coding means for separating said dc components, said more important alternating components, and said less important alternating components; memory means for storing said dc components, said more important alternating components and said less important alternating components and addresses of said components; means responsive to said memory means for assembling said variable-length words into equal length segments, said variable-length words having lengths shorter than a predetermined length being combined with portions of said variable-length words having longer length than said predetermined length to form said equal length segments; a control circuit responsive to said block transform coded signal for controlling said separating means, said memory means and said assembling means; signal combining means coupled to said assembling means for combining a plurality of said equal length segments into superblocks; and an address generator coupled to said control circuit for generating an address for each superblock, said address being appended to each superblock.

Claim 6

A coder for a digital processing system of block, transform coded signals, said transform coded signals having coefficients representing dc components, more important alternating components, and less important alternating components, said coder comprising: quantizing and coding means for quantizing said block transform coded signals and for coding said signals into variable-length words; means coupled to said quantizing and coding means for separating said dc components, said more important alternating components, and said less important alternating components; memory means for storing said dc components, said more important alternating components and said less important alternating components and addresses of said components; means responsive to said memory means for assembling said variable-length words into equal length segments, said variable-length words having lengths shorter than a predetermined length being combined with portions of said variable-length words having longer length than said predetermined length to form said equal length segments; a control circuit responsive to said block transform coded signal for controlling said separating means, said memory means and said assembling means; signal combining means coupled to said assembling means for combining a plurality of said equal length segments into superblocks; and an address generator coupled to said control circuit for generating an address for each superblock, said address being appended to each superblock.

Claim 7

The coder of claim 4 wherein said memory means includes at least one first-in-first-out memory.

Claim 8

The coder of claim 5 wherein said memory includes individual first-in-first-out memory means for said more important alternating components and said less important alternating components.

Claim 9

The method of claim 1 further including the step of positioning said address word at an end of said superblock.

Claim 10

The coder of claim 4 wherein, said memory means further comprises means for measuring memory capacity and generating a control signal responsive to memory utilization, said control signal being coupled to said quantizing and coding means.

Claim 11

The coder of claim 8 wherein, said quantizing and coding means further comprises a controllable quantizer having a characteristic controllably varied by said control signal.