Nonvolatile microprocessor with predetermined state on power-down

Claim 2

A microprocessor, comprising: a power supply input terminal; an external clock input terminal; a battery input terminal; programmable logic, wherein elements of said programmable logic are connected to a reset node, such that a predetermined number of internal clock cycles after a reset signal at said reset node will bring said programmable logic to a known state; an internal clock generator circuit: and clock intercept logic, said clock intercept logic connected to disconnect said programmable logic from the external clock input terminal when power failure at said power supply input terminal is detected, to provide said reset signal to said elements of said programmable logic, and to activate said internal clock generator circuit to provide clocking signals to said programmable logic until said predetermined number of internal clock cycles have occurred.

Claim 3

An integrated circuit, comprising: a power supply input terminal; an external clock input terminal; an internal clock a plurality of logic elements, wherein some, but not all, of said logic elements are connected to be controlled by a reset signal, such that a predetermined number of internal clock cycles, independent of any external clock signals at said external clock input terminal, after activation of said reset signal will bring all of said logic elements to a known state; and power-failure-handling logic, connected to, when power failure at said power supply input is detected, provide said reset signal, and said predetermined number of internal clock cycles thereafter, to said logic elements.

Claim 4

An integrated circuit, comprising: a power supply input terminal; an external clock input terminal; an internal clock a plurality of logic elements, wherein some, but not all, of said logic elements are connected to be controlled by a reset signal, such that a predetermined number of internal clock cycles, independent of any external clock signals at said external clock input terminal, after activation of said reset signal will bring all of said logic elements to a known state; and power-failure-handling logic, connected to, when power failure at said power supply input is detected, provide said reset signal, and said predetermined number of internal clock cycles thereafter, to said logic elements.

Claim 5

A nonvolatile microprocessor-based system, comprising: a system power supply line; a clock line which carries external clock signals; a microprocessor, operatively connected to said system power supply line and to said clock line, comprising programmable logic and logic elements connected to receive a reset signal, such that activation of said reset signal, plus a predetermined number of clock cycles thereafter, will bring all of said programmable logic to a known state; and a battery, connected to provide a backup power supply voltage to said microprocessor if the voltage on said system power supply line falls below a first predetermined level; wherein said microprocessor includes local clock logic, operatively connected to said logic elements, which, when said voltage on said system power supply line falls below a second predetermined level, activates said reset signal and provides said predetermined number of clock cycles thereafter independent of any external clock signals on said clock line.

Claim 6

A nonvolatile microprocessor-based system, comprising: a system power supply line; a clock line which carries external clock signals; a microprocessor, operatively connected to said system power supply line and to said clock line, comprising programmable logic and logic elements connected to receive a reset signal, such that activation of said reset signal, plus a predetermined number of clock cycles thereafter, will bring all of said programmable logic to a known state; and a battery, connected to provide a backup power supply voltage to said microprocessor if the voltage on said system power supply line falls below a first predetermined level; wherein said microprocessor includes local clock logic, operatively connected to said logic elements, which, when said voltage on said system power supply line falls below a second predetermined level, activates said reset signal and provides said predetermined number of clock cycles thereafter independent of any external clock signals on said clock line.

Claim 7

The microprocessor of claim 1, further comprising integrated memory, connected to receive power from said battery input terminal when the power supply voltage at said power supply input terminal fails, so that data in said integrated memory remains valid even after the power supply has failed and recovered.

Claim 8

The microprocessor of claim 1, further comprising integrated memory, including six-transistor static random-access memory cells, connected to receive power from said battery input terminal when the power supply voltage at said power supply input terminal fails, so that data in said integrated memory remains valid even after the system power supply has failed and recovered.

Claim 9

The integrated circuit of claim 2, further comprising on-chip memory, connected to receive power from said battery input terminal when the power supply voltage at said power supply input terminal fails, so that data in said on-chip memory remains valid even after the system power supply has failed and recovered.

Claim 10

The microprocessor of claim 1, wherein said predetermined number of clock cycles is at least two.

Claim 11

The microprocessor of claim 1, wherein said predetermined number of clock cycles is in the range of 10-100, inclusive.

Claim 12

The microprocessor of claim 1, wherein said predetermined number of clock cycles is more than 30.

Claim 13

The microprocessor of claim 1, further comprising power-fail-detect circuitry connected to detect the onset of power failure at said power supply input terminal.

Claim 14

The integrated circuit of claim 2, wherein said predetermined number of clock cycles is at least two.

Claim 15

The integrated circuit of claim 2, wherein said predetermined number of clock cycles is more than 30.

Claim 16

The integrated circuit of claim 2, further comprising power-fail-detect circuitry connected to detect the onset of power failure at the power supply input terminal.

Claim 17

The system of claim 3, wherein said microprocessor further comprises integrated memory, connected to receive power from said battery input terminal when the system power supply line voltage fails, so that data in said integrated memory remains valid even after the system power supply has failed and recovered.

Claim 18

The system of claim 3, further comprising a random-access memory, packaged together with said microprocessor, said memory being connected to receive a power supply from said microprocessor and not being directly connected to said system power supply line.

Claim 19

The system of claim 3, wherein said predetermined number of clock cycles is in the range of 3-300, inclusive.

Claim 20

The system of claim 3, further comprising power-fail-detect circuitry connected to detect the onset of failure in said system power supply.

Claim 21

An integrated circuit, comprising: a subcircuit having at least two states; a power fail detector; an internal clock; an external clock input terminal coupled to said subcircuit; a switching subcircuit connected to said power fail detector, said internal clock, said external clock input terminal, and said subcircuit; wherein a signal from said power fail detector to said switching subcircuit drives said switching subcircuit to turn on said internal clock, decouple said external clock input terminal from said subcircuit, to couple said subcircuit to said internal clock, and to turn off said internal clock after a predetermined number of internal clock cycles.

Claim 22

An integrated circuit, comprising: a subcircuit having at least two states; a power fail detector; an internal clock; an external clock input terminal coupled to said subcircuit; a switching subcircuit connected to said power fail detector, said internal clock, said external clock input terminal, and said subcircuit; wherein a signal from said power fail detector to said switching subcircuit drives said switching subcircuit to turn on said internal clock, decouple said external clock input terminal from said subcircuit, to couple said subcircuit to said internal clock, and to turn off said internal clock after a predetermined number of internal clock cycles.

Claim 23

The circuit of claim 18, wherein: said power fail detector sends a reset signal to said subcircuit when a power failure is detected; and said predetermined number of internal clock cycles following a reset signal drives said subcircuit to a predetermined state.