Method and apparatus for self-timed digital data transfer and bus arbitration

Abstract

Abstract A self-timed bus arbitration and digital data transfer system is provided for a computer network having multiple master and slave devices sharing a digital data bus. Each master device includes a bus arbitration logic circuit having a time delay element. Each master contending for access to the data bus outputs an identifier on signal lines connecting the master devices. After a period of time comprising the slowest master's operational delay, the bus arbitration circuits determine, on a prioritized basis, which particular master shall have access to the data bus at that time. Upon gaining access, the particular master provides a request signal on a control line connecting the master and slave devices and provides an address on an address bus that may be multiplexed with the data bus. After each slave has decoded the address, as determined by the slowest slave's delay, an acknowledge signal is provided on the control line to the particular master so that data transfer may proceed to/from the selected slave. When the data transfer is complete, the selected slave signals the particular master to release the data bus for subsequent operations. Bus arbitration for a subsequent operation may be performed during the current data transfer. All operations are self-timed in that they do not require a bus clock, but they are constrained through wire-OR logic circuitry by the slowest device connected to the system, which includes all delays resulting from bus length, buffers, and environmental conditions.

Inventors

• 👤 David W. Best

Bibliographic Details