Method and system for transmitting HDLC data via ATM network

Claim 5

The method of transmitting HDLC data as claimed in claim 2, wherein a predetermined number of consecutive "1"s are inserted in the HDLC data to indicate an abort from a high-level data link control system, said step (a) further deletes the predetermined number of consecutive "1"s of the HDLC data and inserts abort information in a control bit within the ATM cell to indicate the abort, and said step (c) inserts the predetermined number of "1"s to the disassembled ATM cells depending on the abort information of the control bit to restore the original HDLC data.

Claim 6

The method of transmitting HDLC data as claimed in claim 3, wherein the ATM cell includes an ATM header and an information field, and the control bit is provided in an adaptation header within the information field of the ATM cell.

Claim 9

The method of transmitting HDLC data as claimed in claim 5, wherein the ATM cell includes an ATM header and an information field, and the control bit is provided in an adaptation header within the information field of the ATM cell.

Claim 12

The method of transmitting HDLC data as claimed in claim 7, wherein predetermined bits of the adaptation trailer are used to indicate a region of the data field occupied by valid data.

Claim 13

An ATM cell processing system for generating ATM cells from HDLC data which is in conformance with a high-level data link control procedure to transmit the ATM cells to an asynchronous transfer mode network and for restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, said ATM cell processing system comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data without the flags and for transmitting the ATM cells without the flags via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; and flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data.

Claim 14

An ATM cell processing system for generating ATM cells from HDLC data which is in conformance with a high-level data link control procedure to transmit the ATM cells to an asynchronous transfer mode network and for restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, said ATM cell processing system comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data without the flags and for transmitting the ATM cells without the flags via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; and flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data.

Claim 15

An ATM cell processing system for generating ATM cells from HDLC data which is in conformance with a high-level data link control procedure to transmit the ATM cells to an asynchronous transfer mode network and for restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, wherein a "0" is inserted after five consecutive "1"s of the HDLC data to prevent a bit pattern identical to that of the flag from occurring within a frame of the HDLC data, said ATM cell processing system comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data and for transmitting the ATM cells via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data; zero deleting means, coupled between said flag deleting means and said ATM cell assembling means, for deleting each "0" inserted after five consecutive "1"s of the HDLC data; and zero inserting means, coupled between said ATM cell disassembling means and said flag inserting means, for inserting a "0" to the disassembled ATM cells to restore the original HDLC data.

Claim 16

An ATM cell processing system for generating ATM cells from HDLC data which is in conformance with a high-level data link control procedure to transmit the ATM cells to an asynchronous transfer mode network and for restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, wherein a "0" is inserted after five consecutive "1"s of the HDLC data to prevent a bit pattern identical to that of the flag from occurring within a frame of the HDLC data, said ATM cell processing system comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data and for transmitting the ATM cells via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data; zero deleting means, coupled between said flag deleting means and said ATM cell assembling means, for deleting each "0" inserted after five consecutive "1"s of the HDLC data; and zero inserting means, coupled between said ATM cell disassembling means and said flag inserting means, for inserting a "0" to the disassembled ATM cells to restore the original HDLC data.

Claim 17

The ATM cell processing system as claimed in claim 10, wherein a predetermined number of consecutive "1"s are inserted in the HDLC data to indicate an abort from a high-level data link control system, and said ATM cell processing system further comprises: abort detecting means, coupled between said flag deleting means and said ATM cell assembling means, for detecting the predetermined number of consecutive "1"s of the HDLC data and inserting abort information in a control bit within the ATM cell to indicate the abort; and abort adding means, coupled between said ATM cell disassembling means and said flag inserting means, for adding the predetermined number of "1"s to the disassembled ATM cells depending on the abort information of the control bit to restore the original HDLC data.

Claim 18

The ATM cell processing system as claimed in claim 11, wherein the ATM cell includes an ATM header and an information field, and the control bit is provided in an adaptation header within the information field of the ATM cell.

Claim 19

An ATM cell processing system for generating ATM cells from HDLC data which is in conformance with a high-level data link control procedure to transmit the ATM cells to an asynchronous transfer mode network and for restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, wherein a predetermined number of consecutive "1"s are inserted in the HDLC data to indicate an abort from a high-level data link control system, said ATM cell processing system comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data and for transmitting the ATM cells via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data; abort detecting means, coupled between said flag deleting means and said ATM cell assembling means, for detecting the predetermined number of consecutive "1"s of the HDLC data and inserting abort information in a control bit within the ATM cell to indicate the abort; and abort adding means, coupled between said ATM cell disassembling means and said flag inserting means, for adding the predetermined number of "1"s to the disassembled ATM cells depending on the abort information of the control bit to restore the original HDLC data.

Claim 20

An ATM cell processing system for generating ATM cells from HDLC data which is in conformance with a high-level data link control procedure to transmit the ATM cells to an asynchronous transfer mode network and for restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, wherein a predetermined number of consecutive "1"s are inserted in the HDLC data to indicate an abort from a high-level data link control system, said ATM cell processing system comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data and for transmitting the ATM cells via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data; abort detecting means, coupled between said flag deleting means and said ATM cell assembling means, for detecting the predetermined number of consecutive "1"s of the HDLC data and inserting abort information in a control bit within the ATM cell to indicate the abort; and abort adding means, coupled between said ATM cell disassembling means and said flag inserting means, for adding the predetermined number of "1"s to the disassembled ATM cells depending on the abort information of the control bit to restore the original HDLC data.

Claim 21

The ATM cell processing system as claimed in claim 13, wherein the ATM cell includes an ATM header and an information field, and the control bit is provided in an adaptation header within the information field of the ATM cell.

Claim 22

The ATM cell processing system as claimed in claim 9, wherein the ATM cell includes an ATM header and an information field, said information field includes an adaptation header, a data field and an adaptation trailer, and predetermined bits of the adaptation header are used to indicate a position of each ATM cell in a series of the ATM cells which are transmitted via the asynchronous transfer mode network.

Claim 23

The ATM cell processing system as claimed in claim 15, wherein predetermined bits of the adaptation trailer are used to indicate a region of the data field occupied by valid data.

Claim 24

The ATM cell processing system as claimed in claim 9, wherein the HDLC data is received from a terminal equipment, and said ATM cell processing system forms a part of a terminal adapter which is coupled between the terminal equipment and the asynchronous transfer mode network.

Claim 25

A communication system comprising: an asynchronous transfer mode network; a plurality of terminal adapters coupled to the asynchronous transfer mode network; and a terminal equipment, coupled to each of the terminal adapters, for communicating with each terminal adapter employing a high-level data link control procedure, each of said terminal adapters including an ATM cell processing part for generating ATM cells from HDLC data which is in conformance with the high-level data link control procedure and is received from the terminal equipment to transmit the ATM cells to the asynchronous transfer mode network and restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, said ATM cell processing part comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data without the flags and for transmitting the ATM cells without the flags via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; and flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data.

Claim 26

A communication system comprising: an asynchronous transfer mode network; a plurality of terminal adapters coupled to the asynchronous transfer mode network; and a terminal equipment, coupled to each of the terminal adapters, for communicating with each terminal adapter employing a high-level data link control procedure, each of said terminal adapters including an ATM cell processing part for generating ATM cells from HDLC data which is in conformance with the high-level data link control procedure and is received from the terminal equipment to transmit the ATM cells to the asynchronous transfer mode network and restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, said ATM cell processing part comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data without the flags and for transmitting the ATM cells without the flags via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; and flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data.

Claim 27

A communication system, comprising: an asynchronous transfer mode network; a plurality of terminal adapters coupled to the asynchronous transfer mode network; and a terminal equipment, coupled to each of the terminal adapters, for communicating with each terminal adapter employing a high-level data link control procedure, each of said terminal adapters including an ATM cell processing part for generating ATM cells from HDLC data which is in conformance with the high-level data link control procedure and is received from the terminal equipment to transmit the ATM cells to the asynchronous transfer mode network and restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, wherein a "0" is inserted after five consecutive "1"s of the HDLC data to prevent a bit pattern identical to that of the flag from occurring within a frame of the HDLC data, said ATM cell processing part comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data without the flags and for transmitting the ATM cells without the flags via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data; zero deleting means, coupled between said flag deleting means and said ATM cell assembling means, for deleting each "0" inserted after five consecutive "1"s of the HDLC data; and zero inserting means, coupled between said ATM cell disassembling means and said flag inserting means, for inserting a "0" to the disassembled ATM cells to restore the original HDLC data.

Claim 28

A communication system, comprising: an asynchronous transfer mode network; a plurality of terminal adapters coupled to the asynchronous transfer mode network; and a terminal equipment, coupled to each of the terminal adapters, for communicating with each terminal adapter employing a high-level data link control procedure, each of said terminal adapters including an ATM cell processing part for generating ATM cells from HDLC data which is in conformance with the high-level data link control procedure and is received from the terminal equipment to transmit the ATM cells to the asynchronous transfer mode network and restoring the HDLC data from the ATM cells which are received from the asynchronous transfer mode network, wherein a "0" is inserted after five consecutive "1"s of the HDLC data to prevent a bit pattern identical to that of the flag from occurring within a frame of the HDLC data, said ATM cell processing part comprising: flag deleting means for deleting at least flags from the HDLC data; ATM cell assembling means, coupled to said flag deleting means, for assembling ATM cells from the HDLC data without the flags and for transmitting the ATM cells without the flags via the asynchronous transfer mode network; ATM cell disassembling means, coupled to the asynchronous transfer mode network, for disassembling the ATM cells which are received via the asynchronous transfer mode network; flag inserting means, coupled to said ATM cell disassembling means, for inserting at least flags to the disassembled ATM cells to restore the original HDLC data; zero deleting means, coupled between said flag deleting means and said ATM cell assembling means, for deleting each "0" inserted after five consecutive "1"s of the HDLC data; and zero inserting means, coupled between said ATM cell disassembling means and said flag inserting means, for inserting a "0" to the disassembled ATM cells to restore the original HDLC data.

Claim 29

The communication system as claimed in claim 19, wherein a predetermined number of consecutive "1"s are inserted in the HDLC data to indicate an abort from a high-level data link control system, and said ATM cell processing part further comprises: abort detecting means, coupled between said flag deleting means and said ATM cell assembling means, for detecting the predetermined number of consecutive "1"s of the HDLC data and inserting abort information in a control bit within the ATM cell to indicate the abort; and abort adding means, coupled between said ATM cell disassembling means and said flag inserting means, for adding the predetermined number of "1"s to the disassembled ATM cells depending on the abort information of the control bit to restore the original HDLC data.