US5231638A
Expired / Lapsed
US
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Error correction control apparatus
Assignee: Fujitsu Ltd
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Filing: 1990-04-05
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Granted: 1993-07-27
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Expires: 2010-04-05
Abstract
Abstract An error correction control apparatus corrects errors based on error correction information contained in transferred information. The error correction control apparatus includes a transfer control part for transferring information on a plurality of tracks in a parallel form, and a plurality of error track pointer circuits. Each of the plurality of error track pointer circuits indicates one of the plurality of tracks having an error to be corrected. Error detectors, detect different types of errors included in the information about a corresponding one of the plurality of tracks and set the plurality of error track pointer circuits to an initial state. An error correction circuit corrects the errors indicated by the based on the error correction information. A reset part selectively resets the plurality of error track pointer circuits based on the reset information.
Inventors
- 👤 Seiju Fujiki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:48
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
228 words
An error correction control apparatus, comprising: transfer control means for transferring information about a plurality of tracks in a parallel form, said information including data and reset information; a plurality of error track pointer circuits each indicating one of said plurality of tracks having an error to be corrected; error detecting means, connected to each of said plurality of error track pointer circuits, for detecting different types of errors included in said information about a corresponding one of said plurality of tracks and for setting said plurality of error track pointer circuits to a set state; error correcting means, coupled to said plurality of error track pointer circuits, for correcting said errors indicated by said plurality of error track pointer circuits on the basis of error correction information included in said information about said plurality of tracks, said error correcting means including generating means for generating a request for said transfer control means to transfer said information again and reset means, coupled to said error detecting means and said error correcting means, said reset means for selectively resetting or not resetting any combination of said plurality of error track pointer circuits based on reset information included in said information about said plurality of tracks, said reset means including means for selecting said any combination based on how many times said request is generated from said request generating means.
Claim 2
Dependent Claim
228 words
An error correction control apparatus, comprising: transfer control means for transferring information about a plurality of tracks in a parallel form, said information including data and reset information; a plurality of error track pointer circuits each indicating one of said plurality of tracks having an error to be corrected; error detecting means, connected to each of said plurality of error track pointer circuits, for detecting different types of errors included in said information about a corresponding one of said plurality of tracks and for setting said plurality of error track pointer circuits to a set state; error correcting means, coupled to said plurality of error track pointer circuits, for correcting said errors indicated by said plurality of error track pointer circuits on the basis of error correction information included in said information about said plurality of tracks, said error correcting means including generating means for generating a request for said transfer control means to transfer said information again and reset means, coupled to said error detecting means and said error correcting means, said reset means for selectively resetting or not resetting any combination of said plurality of error track pointer circuits based on reset information included in said information about said plurality of tracks, said reset means including means for selecting said any combination based on how many times said request is generated from said request generating means.
Claim 3
Dependent Claim
67 words
An error correction control apparatus as claimed in claim 1, wherein said reset means comprises counter means for counting a number of times that said request is generated from said request generating means and for generating a counter value, and wherein said selecting means selects any combination of said plurality of error track pointer circuits to be reset based on said counter value from said counter means.
Claim 4
Dependent Claim
157 words
An error correction control apparatus as claimed in claim 1, wherein said reset means comprises: detecting means for detecting predetermined frame data included in said information and for generating a reset signal each time said predetermined frame data is detected; generating means for generating mode signals corresponding to said different types of errors based on said reset information included in said information about said plurality of tracks, one of said mode signals being related to a corresponding one of said error track pointer circuits; and gate means, coupled to said detecting means and said generating means, for performing a logic AND operation between said reset signal and each of said mode signals and for outputting a logic AND operation result for each of said mode signals to a corresponding one of said plurality of error track pointer circuits so that each of said plurality of error track pointer circuits is reset by said logic AND operation result.
Claim 5
Dependent Claim
19 words
An error correction control apparatus as claimed in claim 3, wherein said predetermined frame data occurs at predetermined intervals.
Claim 6
Dependent Claim
49 words
An error correction control apparatus as claimed in claim 3, wherein said information on said plurality of tracks data frames having a predetermined length and re-synchronous frame patterns each synchronizing one of said plurality of data frames, and wherein said predetermined frame data corresponds to said re-synchronous frame patterns.
Claim 7
Dependent Claim
79 words
An error correction control apparatus as claimed in claim 1, wherein said reset means comprises: storage means for storing data indicating combinations of said plurality of error track pointer circuits to be reset; and address generating means, coupled to said storage means, for deriving an address signal from said reset information included in said information on said plurality of tracks, said address signal indicating one of said combinations of said plurality of error track pointer circuits to be reset.
Claim 8
Dependent Claim
19 words
An error correction control apparatus as claimed in claim 6, wherein said storage means comprises a read only memory.
Claim 9
Dependent Claim
17 words
An error correction control apparatus as claimed in claim 6, wherein said storage means comprises a microprogram.
Claim 10
Dependent Claim
211 words
An error correction control apparatus as claimed in claim 1, wherein said reset means comprises: decision means, for determining whether a corresponding one of said plurality of pointer circuits should be reset on the basis of a corresponding decision and for generating a decision signal; detecting means for detecting predetermined frame data included in said information and for generating a reset signal each time said predetermined frame data is selected; generating means for generating mode signals corresponding to said different types of errors on the basis of said reset information included in said information on said plurality of tracks, one of said mode signals being related to a corresponding one of said error track pointer circuits; first gate means, coupled to said decision means and said detecting means, for performing a logic OR operation between said decision signal and said reset signal and for generating a logic OR operation result; and second gate means, coupled to said first gate means and said generating means, for performing a logic AND operation between a corresponding one of said mode signals and said logic OR operation result and for outputting a logic AND operation result so that a corresponding one of said error track pointer circuits is reset by said logic AND operation result.
Claim 11
Dependent Claim
79 words
An error correction control apparatus as claimed in claim 1, wherein said error detecting means comprises detectors each relating to a corresponding one of the different types of errors, and each of said detectors detects said corresponding one of the different types of errors and generates a set signal, and wherein said set signal is supplied to a corresponding one of said error track pointer circuits so that said corresponding one of said error track pointer circuits is reset.
Claim 12
Dependent Claim
20 words
An error correction control apparatus as claimed in claim 1, wherein each of said error track pointers comprises a flip-flop.
Claim 13
Dependent Claim
20 words
An error correction control apparatus as claimed in claim 1, wherein each of said error track pointers comprises a register.
Claim 14
Dependent Claim
27 words
An error correction control apparatus as claimed in claim 1, wherein said information is data read out from said plurality of tracks formed on a magnetic tape.
Claim 15
Dependent Claim
49 words
An error correction control apparatus as claimed in claim 1, further comprising an internal pointer wherein said internal pointer is set and reset by a syndrome process, and said error correcting means corrects said errors indicated by said internal pointer in addition to said plurality of error track pointers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-26 | 1997-01-25 | 1997-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-26 | 2001-01-25 | 2001-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-26 | 2005-01-25 | 2005-07-27 | $7700.00 | Window Closed / Lapsed |