Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
451 words
An error data correcting system in which a series of n data words W 1 through W n each including m bits has associated therewith a P check code ##EQU24## and a Q check code ##EQU25## the system for correcting erroneous data words W c , and W d , to produce correct data words W c and W d (l≦c<d≦n), the system generating a first syndrome value ##EQU26## and a second syndrome value ##EQU27## when the series of data words includes erroneous data words W c' , and W d' , respectively, the system comprising: a first input terminal for receiving said series of data words and said associated first and second syndrome values; an auxiliary matrix circuit for multiplying said first syndrome value by an auxiliary matrix T - (n+1) ; a T matrix operation circuit for receiving the output of said auxiliary matrix circuit and for shifting said received value c positions to output T c- (n+1) S 2 ; a P register coupled to said first input terminal for receiving said first syndrome value; switch means for selectively coupling the output of said P register to the input of said T matrix operation circuit to cause said T matrix operation circuit to store S 1 +T c- (n+1) S 2 ; a second input terminal for receiving an error data pointer; an error word control circuit coupled to said second input terminal for generating an interval signal k=d-c corresponding to the series positional difference between said second error word W d' and said first error word W c' in response to said error data pointer; a first gate circuit coupled to the output of said T matrix operation circuit; a matrix generating circuit for receiving said interval signal k from said error word control circuit, for generating a matrix signal corresponding to a specific bit in the output of said T matrix operation circuit, and for supplying said matrix signal to said first gate circuit, said first gate circuit for combining said output of said T matrix operation circuit (T c- (n+1) S 2 with said matrix signal k to generate a second corrected data word W de ; a first buffer for storing said second corrected data word W de ; a second buffer coupled to said P register for receiving and storing said first syndrome value S 1 ; and means coupled to said first buffer for receiving said second corrected data word W de and to said second buffer for receiving said first syndrome value S 1 and for combining said second corrected data word W de and said first syndrome value S 1 to generate a first corrected data word W ce .
Claim 2
Dependent Claim
451 words
An error data correcting system in which a series of n data words W 1 through W n each including m bits has associated therewith a P check code ##EQU24## and a Q check code ##EQU25## the system for correcting erroneous data words W c , and W d , to produce correct data words W c and W d (l≦c<d≦n), the system generating a first syndrome value ##EQU26## and a second syndrome value ##EQU27## when the series of data words includes erroneous data words W c' , and W d' , respectively, the system comprising: a first input terminal for receiving said series of data words and said associated first and second syndrome values; an auxiliary matrix circuit for multiplying said first syndrome value by an auxiliary matrix T - (n+1) ; a T matrix operation circuit for receiving the output of said auxiliary matrix circuit and for shifting said received value c positions to output T c- (n+1) S 2 ; a P register coupled to said first input terminal for receiving said first syndrome value; switch means for selectively coupling the output of said P register to the input of said T matrix operation circuit to cause said T matrix operation circuit to store S 1 +T c- (n+1) S 2 ; a second input terminal for receiving an error data pointer; an error word control circuit coupled to said second input terminal for generating an interval signal k=d-c corresponding to the series positional difference between said second error word W d' and said first error word W c' in response to said error data pointer; a first gate circuit coupled to the output of said T matrix operation circuit; a matrix generating circuit for receiving said interval signal k from said error word control circuit, for generating a matrix signal corresponding to a specific bit in the output of said T matrix operation circuit, and for supplying said matrix signal to said first gate circuit, said first gate circuit for combining said output of said T matrix operation circuit (T c- (n+1) S 2 with said matrix signal k to generate a second corrected data word W de ; a first buffer for storing said second corrected data word W de ; a second buffer coupled to said P register for receiving and storing said first syndrome value S 1 ; and means coupled to said first buffer for receiving said second corrected data word W de and to said second buffer for receiving said first syndrome value S 1 and for combining said second corrected data word W de and said first syndrome value S 1 to generate a first corrected data word W ce .
Claim 3
Dependent Claim
88 words
An error data correcting system according to claim 1 wherein said receiving and combining means comprises: an adder coupled to said first buffer for receiving said second corrected data word W ce ; and a second gate circuit coupled to said second buffer and said adder to selectively supply said first syndrome value S 1 to said adder to enable said adder to add said first syndrome value S 1 and said second corrected data word W de to generate said first corrected data word W ce .
Claim 4
Dependent Claim
92 words
An error data correcting system according to claim 2 further including: an output terminal; means for transferring said series of data words W l through W n including said error data words W c' and W d' from said input terminal to said output terminal; and means for replacing said first and second error data words W c' and W d' with said first and second corrected data words W ce and W de , respectively, as said series of data words are transferred from said input terminal to said output terminal.
Claim 5
Dependent Claim
17 words
An error data correcting system according to claim 3 wherein said transferring means comprises a delay circuit.
Claim 6
Dependent Claim
142 words
An error data correcting system according to claim 1 wherein said T matrix operation circuit comprises: a serial to parallel converter for converting said output of said auxiliary matrix to a plurality of parallel data words; a plurality of shift registers, each of said shift registers being associated with a different one of said plurality of parallel data words; a plurality of adder circuits, each of said adder circuits being connected between a different pair of said shift registers; a pluraity of gate circuits in one-to-one association with said plurality of parallel data words, each of said gate circuits being coupled to said adder circuit preceding said shift register associated with said parallel data word associated with said gate circuit; and means for controlling said gate circuits to enable the selective transfer of said parallel data words to said associated shift registers.