← Back to Patent Explorer
US4368533A Expired / Lapsed US ⏱️ 0.0 years remaining

Error data correcting system

Assignee: Toshiba Corp
•
Filing: 1980-04-28
•
Granted: 1983-01-11
•
Expires: 2000-04-28
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A data input signal having n data words and two check words expressed by W 1 to WnPQ as one block is applied through a T - (n+1) operation circuit to a Q register where it is processed for a Q decoding. The data input signal is applied to a P register where it is processed for a P decode. Through those processings, the syndrome S 1 derived from a P register and T c- (n+1) S 2 obtained by shifting the Q 1 register in accordance with the first error word summed by the Q register. S 1 +T c- (n+1) S 2 as the result of the addition is multiplied by the matrix data for decoding a specific bit, which is derived from a matrix generating circuit, in a multiplier gate circuit, so that it is decoded as the corrected data W de of the second error word Wd'. Then, the corrected data Wce is applied to a buffer circuit. In this case, the matrix generating circuit generates matrix data for decoding a specific bit by using interval data k representing the interval between the first error word Wc' and the second error word Wd'. The S 1 is inputted into the buffer circuit. The W dc and the corrected data W ce (=S 1 +W de ) of the first error word W c' are read out from the buffer circuits, through gate circuits for multiplication and a gate circuit for addition. Those are added to the corresponding information words Wc and Wd of the input data signal coming through one block delay, by a gate circuit for addition, as that the error data is corrected.

Inventors

  • 👤 Tadashi Kojima

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 08:06
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1813

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 451 words
An error data correcting system in which a series of n data words W 1 through W n each including m bits has associated therewith a P check code ##EQU24## and a Q check code ##EQU25## the system for correcting erroneous data words W c , and W d , to produce correct data words W c and W d (l≦c<d≦n), the system generating a first syndrome value ##EQU26## and a second syndrome value ##EQU27## when the series of data words includes erroneous data words W c' , and W d' , respectively, the system comprising: a first input terminal for receiving said series of data words and said associated first and second syndrome values; an auxiliary matrix circuit for multiplying said first syndrome value by an auxiliary matrix T - (n+1) ; a T matrix operation circuit for receiving the output of said auxiliary matrix circuit and for shifting said received value c positions to output T c- (n+1) S 2 ; a P register coupled to said first input terminal for receiving said first syndrome value; switch means for selectively coupling the output of said P register to the input of said T matrix operation circuit to cause said T matrix operation circuit to store S 1 +T c- (n+1) S 2 ; a second input terminal for receiving an error data pointer; an error word control circuit coupled to said second input terminal for generating an interval signal k=d-c corresponding to the series positional difference between said second error word W d' and said first error word W c' in response to said error data pointer; a first gate circuit coupled to the output of said T matrix operation circuit; a matrix generating circuit for receiving said interval signal k from said error word control circuit, for generating a matrix signal corresponding to a specific bit in the output of said T matrix operation circuit, and for supplying said matrix signal to said first gate circuit, said first gate circuit for combining said output of said T matrix operation circuit (T c- (n+1) S 2 with said matrix signal k to generate a second corrected data word W de ; a first buffer for storing said second corrected data word W de ; a second buffer coupled to said P register for receiving and storing said first syndrome value S 1 ; and means coupled to said first buffer for receiving said second corrected data word W de and to said second buffer for receiving said first syndrome value S 1 and for combining said second corrected data word W de and said first syndrome value S 1 to generate a first corrected data word W ce .
Claim 2
Dependent Claim 451 words
An error data correcting system in which a series of n data words W 1 through W n each including m bits has associated therewith a P check code ##EQU24## and a Q check code ##EQU25## the system for correcting erroneous data words W c , and W d , to produce correct data words W c and W d (l≦c<d≦n), the system generating a first syndrome value ##EQU26## and a second syndrome value ##EQU27## when the series of data words includes erroneous data words W c' , and W d' , respectively, the system comprising: a first input terminal for receiving said series of data words and said associated first and second syndrome values; an auxiliary matrix circuit for multiplying said first syndrome value by an auxiliary matrix T - (n+1) ; a T matrix operation circuit for receiving the output of said auxiliary matrix circuit and for shifting said received value c positions to output T c- (n+1) S 2 ; a P register coupled to said first input terminal for receiving said first syndrome value; switch means for selectively coupling the output of said P register to the input of said T matrix operation circuit to cause said T matrix operation circuit to store S 1 +T c- (n+1) S 2 ; a second input terminal for receiving an error data pointer; an error word control circuit coupled to said second input terminal for generating an interval signal k=d-c corresponding to the series positional difference between said second error word W d' and said first error word W c' in response to said error data pointer; a first gate circuit coupled to the output of said T matrix operation circuit; a matrix generating circuit for receiving said interval signal k from said error word control circuit, for generating a matrix signal corresponding to a specific bit in the output of said T matrix operation circuit, and for supplying said matrix signal to said first gate circuit, said first gate circuit for combining said output of said T matrix operation circuit (T c- (n+1) S 2 with said matrix signal k to generate a second corrected data word W de ; a first buffer for storing said second corrected data word W de ; a second buffer coupled to said P register for receiving and storing said first syndrome value S 1 ; and means coupled to said first buffer for receiving said second corrected data word W de and to said second buffer for receiving said first syndrome value S 1 and for combining said second corrected data word W de and said first syndrome value S 1 to generate a first corrected data word W ce .
Claim 3
Dependent Claim 88 words
An error data correcting system according to claim 1 wherein said receiving and combining means comprises: an adder coupled to said first buffer for receiving said second corrected data word W ce ; and a second gate circuit coupled to said second buffer and said adder to selectively supply said first syndrome value S 1 to said adder to enable said adder to add said first syndrome value S 1 and said second corrected data word W de to generate said first corrected data word W ce .
Claim 4
Dependent Claim 92 words
An error data correcting system according to claim 2 further including: an output terminal; means for transferring said series of data words W l through W n including said error data words W c' and W d' from said input terminal to said output terminal; and means for replacing said first and second error data words W c' and W d' with said first and second corrected data words W ce and W de , respectively, as said series of data words are transferred from said input terminal to said output terminal.
Claim 5
Dependent Claim 17 words
An error data correcting system according to claim 3 wherein said transferring means comprises a delay circuit.
Claim 6
Dependent Claim 142 words
An error data correcting system according to claim 1 wherein said T matrix operation circuit comprises: a serial to parallel converter for converting said output of said auxiliary matrix to a plurality of parallel data words; a plurality of shift registers, each of said shift registers being associated with a different one of said plurality of parallel data words; a plurality of adder circuits, each of said adder circuits being connected between a different pair of said shift registers; a pluraity of gate circuits in one-to-one association with said plurality of parallel data words, each of said gate circuits being coupled to said adder circuit preceding said shift register associated with said parallel data word associated with said gate circuit; and means for controlling said gate circuits to enable the selective transfer of said parallel data words to said associated shift registers.

References Cited (Backward Citations)

US3418630A Cited
GB1198510A Cited
GB1224423A Cited
US3629824A Cited
US3697948A Cited
GB1313488A Cited
US3745528A Cited
GB1369725A Cited
US3868632A Cited
GB1468604A Cited
US4052698A Cited
FR2448255A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-01-10 1986-07-12 1987-01-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-01-10 1990-07-12 1991-01-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-01-10 1994-07-12 1995-01-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag