US3868632A — Plural channel error correcting apparatus and met…

Claim 1

Independent Claim 158 words

An error correcting system for correcting up to two channels in error in a multiparallel channel data handling system comprising: an encoding system including cyclic check bit generating means for generating an orthogonally symmetrical check bit for each of said parallel channels, said check bits being entered into said respective channels and being grouped to form a crosschannel check byte; said encoding system further including parity bit generating means for generating parity bits for information bytes formed in a cross-channel direction, means for entering said parity bits into one of said parallel channels; means for decoding said data by means of said parity bits and information bytes formed in the cross-channel direction to detect errors; and means for correcting errors in all the bytes extending along any one or more channels including cyclic means generating a cyclic syndrome vector simultaneously to a parity syndrome vector based on the errors detected in the decoding utilizing only said cross-track bytes.

Claim 2

Dependent Claim 158 words

An error correcting system for correcting up to two channels in error in a multiparallel channel data handling system comprising: an encoding system including cyclic check bit generating means for generating an orthogonally symmetrical check bit for each of said parallel channels, said check bits being entered into said respective channels and being grouped to form a crosschannel check byte; said encoding system further including parity bit generating means for generating parity bits for information bytes formed in a cross-channel direction, means for entering said parity bits into one of said parallel channels; means for decoding said data by means of said parity bits and information bytes formed in the cross-channel direction to detect errors; and means for correcting errors in all the bytes extending along any one or more channels including cyclic means generating a cyclic syndrome vector simultaneously to a parity syndrome vector based on the errors detected in the decoding utilizing only said cross-track bytes.

Claim 3

Dependent Claim 17 words

arranging said bytes into sets of one less than the number of channels of said cross-channel bytes;

Claim 4

Dependent Claim 17 words

arranging said bytes into sets of one less than the number of channels of said cross-channel bytes;

Claim 5

Dependent Claim 65 words

An error correcting system according to claim 1, wherein said parity bit generating means generates another parity bit for each of said groups of check bits forming a cross-channel byte so that said means for decoding is applicable to said cross-track check byte and said means for correcting errors includes the said check bits in any one or two designated channels of siad parallel channels.

Claim 6

Dependent Claim 17 words

generating a check bit signal byte for said N-1 data signal bytes in an orthogonally symmetrical manner;

Claim 7

Dependent Claim 17 words

generating a check bit signal byte for said N-1 data signal bytes in an orthogonally symmetrical manner;

Claim 8

Dependent Claim 43 words

transferring said N-1 data and check bit signal bytes as a signal set over said N channels; repeating (1), (2), and (3) until signals signzls have been transferred; and B. at a receiver for said transferred data signal bytes in each said set,

Claim 9

Dependent Claim 43 words

transferring said N-1 data and check bit signal bytes as a signal set over said N channels; repeating (1), (2), and (3) until signals signzls have been transferred; and B. at a receiver for said transferred data signal bytes in each said set,

Claim 10

Dependent Claim 11 words

generating a check cross-channel byte on said set of cross-channel bytes;

Claim 11

Dependent Claim 11 words

generating a check cross-channel byte on said set of cross-channel bytes;

Claim 12

Dependent Claim 74 words

An error correcting system according to claim 1, wherein said means for generating check bits including means for computing said cross-track check bytes according to the relationship: C TB1 +T2B2 + T3B3 +. . . + Tn BN where T is the companion matrix of an irredicuble binary polynominal g(x) of degree n2 and Ti represents the ith power of the matrix T and Bi represents the n2 data bytes of n1- 1 bits.

Claim 13

Dependent Claim 26 words

An error correcting system according to claim 3, wherein said means for generating check bits includes a shift register which premultiplies the incoming bytes by T.

Claim 14

Dependent Claim 9 words

recording said cross-channel bytes of (2) and (3); and

Claim 15

Dependent Claim 9 words

recording said cross-channel bytes of (2) and (3); and

Claim 16

Dependent Claim 16 words

computing a second check bit signal byte supposedly identical to said transferred check bit signal byte;

Claim 17

Dependent Claim 16 words

computing a second check bit signal byte supposedly identical to said transferred check bit signal byte;

Claim 18

Dependent Claim 20 words

comparing the check bit signal bytes and from said comparison generating an error pattern for signals along a given channel;

Claim 19

Dependent Claim 20 words

comparing the check bit signal bytes and from said comparison generating an error pattern for signals along a given channel;

Claim 20

Dependent Claim 15 words

repeating (1) -(4) until all signals to be recorded in a block have been recorded.

Claim 21

Dependent Claim 15 words

repeating (1) -(4) until all signals to be recorded in a block have been recorded.

Claim 22

Dependent Claim 83 words

An error correcting system according to claim 3, including means in said decoder for computing two syndrome bytes S1 and S2 each of n1- 1 bits according to the relationship: S1 P + P which is derived from modulo 2 addition of the generated parity byte P and the received parity byte P; and S2 C + T1B1+T2B2 +. . . + Tn BN wherein an underlined symbol indicates a byte of said received message corresponding to nonunderlined symbols in said sent measage.

Claim 23

Dependent Claim 39 words

An error correcting system according to claim 5, wherein said means for computing two syndrome bytes S1 and S2 includes feedback shift registers, said shift register for computing S2 being a backward shifting register having a premultiplier Tn .

Claim 24

Dependent Claim 12 words

indicating which channel is said given channel having signals in error; and

Claim 25

Dependent Claim 12 words

indicating which channel is said given channel having signals in error; and

Claim 26

Dependent Claim 15 words

applying said error pattern to correct signals in said given channel for such signal set.

Claim 27

Dependent Claim 15 words

applying said error pattern to correct signals in said given channel for such signal set.

Claim 28

Dependent Claim 88 words

An error correcting system according to claim 1, means supplying error location pointers, said means for decoding includes an N indicator means for providing the control signal N1, N3, and Q in response to error pointers indicating the channel in error, the N1 signal indicates that only one channel pointer or none are on, the N3 signal indicates that more than two channel pointers are on, and the Q output represents the pointers Q0-Q8, and means for inhibiting said control signals Q when N1 or N3 is on.

Claim 29

Dependent Claim 78 words

An error correcting system according to claim 7, wherein said means for decoding further includes means for generating the error track parameters I, i, and j-i from the pointer control signals Q, the error channel parameter I being a new pointer which identifies the first erroneous data channel called the Ith channel, the signals i being generated as binary numbers from the I pointer signals and the j-i signals indicating the responsive distance of the channels in error.

Claim 30

Dependent Claim 26 words

generating an independent check bit signal for each of said bytes including said check bit signal byte as they are being transferred; B-1. at the receiVer,

Claim 31

Dependent Claim 26 words

generating an independent check bit signal for each of said bytes including said check bit signal byte as they are being transferred; B-1. at the receiVer,

Claim 32

Dependent Claim 35 words

combining said independent check bits for all of said bytes in a given signal set with said check bit signal byte for generating first and second error pattern signals respectively for first and second channels;

Claim 33

Dependent Claim 35 words

combining said independent check bits for all of said bytes in a given signal set with said check bit signal byte for generating first and second error pattern signals respectively for first and second channels;

Claim 34

Dependent Claim 80 words

An error correcting system according to claim 8, wherein said means for decoding includes means for generating the error pattern e2 from the S1 and T i S2 inputs controlled by said j-i inputs according to the relationships: e2 Mj i (S1 + T 1 S2) where: Mj i (Id + Tj i ) 1 if j-i not = 0 and j not = 8 Mj i Td if j-i 0 or j 8 and Id is an identity matrix.

Claim 35

Dependent Claim 85 words

An error correcting system according to claim 9, wherein said means for decoding includes means for generating a code pointer Q'' and means for generating a count R, said means for generating a code pointer having the count R, the control signal N1, and e2 as inputs; said code pointer generator generating the code pointer Q'' indicative of a single track in error when said input signal e2 0 and N1 is on, the R count from said ring counter indicating the channel in error.

Claim 36

Dependent Claim 16 words

repeating step (6) for each signal set for indicating which two channels have signals in error;

Claim 37

Dependent Claim 16 words

repeating step (6) for each signal set for indicating which two channels have signals in error;

Claim 38

Dependent Claim 24 words

selectively modifying step (7) to correct signals in two of said channels rather than correcting errors in but one channel for such signal set.

Claim 39

Dependent Claim 24 words

selectively modifying step (7) to correct signals in two of said channels rather than correcting errors in but one channel for such signal set.

Claim 40

Dependent Claim 75 words

An error correcting system according to claim 1, wherein said means for corercting errors in all the bytes extending along any one channel or any two designated channels includes modulo 2 adder circuits for comparing the error patterns S1 and e2 with said channel bytes of information Z0, Z1, Z2, . . . Z7 and producing corrected information in accordance with said error patterns to obtain the corrected information Z0, Z1, . . . Z7.

Claim 41

Independent Claim 27 words

The method of transferring successive N-bit signal bytes through N channels, one signal from each byte in a channel, including the steps of: A. at a transmitter,

Claim 42

Independent Claim 27 words

The method of transferring successive N-bit signal bytes through N channels, one signal from each byte in a channel, including the steps of: A. at a transmitter,

Claim 43

Dependent Claim 44 words

processing said data bytes in each said channel such that the operational relationships between each and every data bit and each and every check bit with respect to said column vector operators remain the same even though the signals are along the respective channels.

Claim 44

Dependent Claim 44 words

processing said data bytes in each said channel such that the operational relationships between each and every data bit and each and every check bit with respect to said column vector operators remain the same even though the signals are along the respective channels.

Claim 45

Dependent Claim 16 words

The method set forth in claim 12 further including the steps of: A-1. at the transmitter,

Claim 46

Dependent Claim 46 words

The method set forth in claim 12 further in said step (2) generating said check bit signal byte in accordance with an identity matrix and N-1 companion matrices, each matrix consisting of n column vector operator signals modulo a selected polynomial; and B-2. at said receiver,

Claim 47

Dependent Claim 94 words

The method set forth in claim 14 further including selecting said independent check bit signal to be a parity signal and selecting a magnetic tape unit having nine tracks with a central one of said tracks being the parity track and the other eight tracks, including the outside tracks, being data tracks, and repeatedly performing said steps (1) through (3), (8) for recording a plurality of successive end bit signal bytes on said tape and repeatedly performing steps (4) through (7) and (9) through (12) for reading back the signals recorded on such tape.

Claim 48

Independent Claim 115 words

The method of operating a multichannel digital signal apparatus, including the steps of: selecting a first group of said channels to sequentially transfer plural sets of data signals, the number of signals in each channel for each set being one less than the number of channels in said first group; for each said set, generating a first check byte having one signal in each channel for said each set of said first group and arranging all signals in each said set including said check byte signals to have orthogonal symmetry; and generating second check signals based on said arranging and supplying said second check signals to a chennal other than said first group of channels.

Claim 49

Independent Claim 115 words

The method of operating a multichannel digital signal apparatus, including the steps of: selecting a first group of said channels to sequentially transfer plural sets of data signals, the number of signals in each channel for each set being one less than the number of channels in said first group; for each said set, generating a first check byte having one signal in each channel for said each set of said first group and arranging all signals in each said set including said check byte signals to have orthogonal symmetry; and generating second check signals based on said arranging and supplying said second check signals to a chennal other than said first group of channels.

Claim 50

Dependent Claim 51 words

The method set forth in claim 16 selecting a polynomial from the Galois Field 2b for said first check byte, where b is the number of channels in said first group and generating said second check signals in a manner not describable in terms of symbols in said Galois Field 2b.

Claim 51

Dependent Claim 35 words

The method set forth in claim 16 including generating said second check signals as parity signals based upon one signal from each of said channels in said first set and aligned in a cross-channel direction.

Claim 52

Independent Claim 112 words

The method of operating a multichannel digital signal transfer system, including the step: selecting first and second independent error correction codes, each having a given error correction capability, said first error correction code exhibiting orthogonal symmetry; dividing the digital signals into sets along the respective channels into a number of signals less than the number of channels; establishing a first check bit byte in accordance with a given orthogonal symmetry and a polynomial in said first error correction code; establishing a second check bit byte in accordance with said second error correction code; and selectively using one or both of said codes to correct errors in a given one of said channels.

Claim 53

Independent Claim 112 words

The method of operating a multichannel digital signal transfer system, including the step: selecting first and second independent error correction codes, each having a given error correction capability, said first error correction code exhibiting orthogonal symmetry; dividing the digital signals into sets along the respective channels into a number of signals less than the number of channels; establishing a first check bit byte in accordance with a given orthogonal symmetry and a polynomial in said first error correction code; establishing a second check bit byte in accordance with said second error correction code; and selectively using one or both of said codes to correct errors in a given one of said channels.

Claim 54

Dependent Claim 117 words

The method set forth in claim 19 including selectively using both of said codes to correct errors and including shifting data signals in the respective sets in a forward direction for processing signals in a so-called forward direction including premultiplying by a matrix T of said polynomial, then repeatedly maTrix mutliplying by a matrix T by shifting in a forward direction and including linear feedback in said shifting in accordance with said polynomial; and selectively processing said signals in a backward direction including premultiplying said signals in the respective sets by a matrix T7 of said polynomial and including matrix multiplying said signals in such sets by T 1 for seven times in a so-called backward direction.

Claim 55

Dependent Claim 83 words

The method set forth in claim 19 further including selecting said first independent error correction code to have orthogonal symmetry in accordance with a given polynomial and arranging column vectors based upon said polynomial in a predetermined manner such that said check bit signals mathematically established said check bit byte in a predetermined relationship to the data signals in a cross-channel direction, a first position being an end position of an array including said data signals and said first check bit byte signals.

Claim 56

Dependent Claim 43 words

The method set forth in claim 21 further including selecting said column vectors to generate error correction and error bit generating matrices for placing siad check bit byte in a central position of said data signals array rather than in said end position.

Claim 57

Independent Claim 163 words

The method of generating a check bit to establish orthogonal symmetry in a set of data and check signal bytes, each byte having N-1 bits and the set having N bytes, N being a positive integer greater than 1, including the following steps: arranging the signals in a rectangular array; selecting one of the diagonals of said rectangular array as a line of symmetry; selecting a bit position of said check byte for a check bit signal to be generated; generating the selected check bit signal by modulo 2 adding signals in the array along selected ones of diagonals transverse to said line of symmetry, the signals on said transverse diagonals being eitehr on said line of symmetry or symmetrically disposed with respect to said line of symmetry; and selecting one of said selected diagonals in accordance with the location of said selected check bit signals in said array and adding said signals symmetrically except for said check bit signal to be generated.

Claim 58

Independent Claim 163 words

The method of generating a check bit to establish orthogonal symmetry in a set of data and check signal bytes, each byte having N-1 bits and the set having N bytes, N being a positive integer greater than 1, including the following steps: arranging the signals in a rectangular array; selecting one of the diagonals of said rectangular array as a line of symmetry; selecting a bit position of said check byte for a check bit signal to be generated; generating the selected check bit signal by modulo 2 adding signals in the array along selected ones of diagonals transverse to said line of symmetry, the signals on said transverse diagonals being eitehr on said line of symmetry or symmetrically disposed with respect to said line of symmetry; and selecting one of said selected diagonals in accordance with the location of said selected check bit signals in said array and adding said signals symmetrically except for said check bit signal to be generated.

Claim 59

Dependent Claim 34 words

The method of claim 23 including generating the selected check bit signal by modulo 2 ending all signals along said selected transverse diagonals except said check bit signal in one of said selected diagonals.

Claim 60

Dependent Claim 40 words

The method of claim 25 further including the step of selecting said check bit position and then selecting all said transverse diagonals in a sequence proceeding from said one transverse diagonal in but one direction along said line of symmetry.

Claim 61

Dependent Claim 240 words

Error correcting apparatus for processing data and check bit signals received from a multichannel signal transfer system, said signals in said channels being grouped into multichannel signal sets having a number of signals along each channel equal to the number of channels, all signals in one channel being a first check bit redundancy portion and one signal of each set in each remaining channel being a signal in a second check bit redundancy portion, said data signals and second check bit redundancy signals exhibiting orthogonal symmetry, the improvement including in combination; first byte signal processing means for calculating said first check bit redundancy based on received signals from said remaining channels and comparing same with received first check bit redundancy signals from said one channel to supply first syndrome signals; second byte signal processing means for each signal set for simultaneously processing one signal from each of said remaining channels to compute said second check bit redundancy and compare a received second redundancy signal with calculated second check bit redundancy to supply second syndrome signals; means storing received signals from said remaining channels; means receiving said syndrome signals and having orthogOnally symmetrical matrix multiplication means to generate an error pattern for signals in error along any one of said channels in one of said signal sets; and means receiving said stored signals and said error pattern for correcting signals in error, if any, along one or more of said channels.

Claim 62

Dependent Claim 240 words

Error correcting apparatus for processing data and check bit signals received from a multichannel signal transfer system, said signals in said channels being grouped into multichannel signal sets having a number of signals along each channel equal to the number of channels, all signals in one channel being a first check bit redundancy portion and one signal of each set in each remaining channel being a signal in a second check bit redundancy portion, said data signals and second check bit redundancy signals exhibiting orthogonal symmetry, the improvement including in combination; first byte signal processing means for calculating said first check bit redundancy based on received signals from said remaining channels and comparing same with received first check bit redundancy signals from said one channel to supply first syndrome signals; second byte signal processing means for each signal set for simultaneously processing one signal from each of said remaining channels to compute said second check bit redundancy and compare a received second redundancy signal with calculated second check bit redundancy to supply second syndrome signals; means storing received signals from said remaining channels; means receiving said syndrome signals and having orthogOnally symmetrical matrix multiplication means to generate an error pattern for signals in error along any one of said channels in one of said signal sets; and means receiving said stored signals and said error pattern for correcting signals in error, if any, along one or more of said channels.

Claim 63

Dependent Claim 172 words

The error correcting apparatus set forth in claim 26 including forward signal processing indicating means and backward signal processing indicating means; means in said second byte signal processing means responsive to said forward processing indicating means to premultiply said data signals on a byte basis by a matrix T based upon a polynomial for said second check bit redundancy portion and effectively forward shifting said signals to multiply by said matrix T and including linear feedback means during said second byte signal processing; means in said second byte signal processing means responsive to said backward byte processing indicating means to premultiply said data signals by the matrix T7 and further having means operating said second byte signal processing means for effectively shifting said signals in a backward direction such that each shift is equal to a matrix multiplication of T 1; and all of the other means in said error correcting apparatus being responsive to said forward and backward indicating means, respectively, to alter operations to accommodate forward and backward signal processing.

Claim 64

Dependent Claim 88 words

The apparatus set forth in claim 27 further including means in said syndrome receiving means indicating when said one channel is in error and operation altering means responsive to indicating that said one channel is in error not to correct said one channel; and means generating an indication of which data channel is in error and said error correcting means being jointly responsive to said second byte signal processing means and said error pointer means to correct data signals in error independent of signals from said one channel.

Claim 65

Dependent Claim 188 words

The error correcting apparatus set forth in claim 26 wherein said second byte signal processing means generates a set of output signals equal to T iS2; error pattern generator means responsive to said T iS2 and to said first byte signal processing means for generating a given error pattern; counter means responsive to the number of bytes being processed to supply an R count; code pointer generator means jointly responsive to said R count and said given error pattern to generate a track-in-error pointer signal; error track parameter generator responsive to said code pointer generator and having error pointer means for generating a set of track-in error pointer signals and error correcting means jointly responsive to said given error pattern and to said track-in-error indicator to correct errors along a given channel wherein said given error pattern is used both to indicate a track in error and the error pattern along such track; and wherein said error correction means is further responsive to said first byte signal processing means to correct a second channel in error in accordance with pointer signals received from said error track parameters generator.

Claim 66

Dependent Claim 147 words

An error correction signal generating system for a multichannel digital transfer system, a first plurality of said channels transferring data representing digital signals, the improvement including in combination: means grouping data representing digital signals along each channel in signal groups having a number of signals equal to a number less than said first plurality; means associating all groups in said channel together as a multichannel signal set; means calculating check bit redundancy signals for all signals in one signal set; means for transmitting a first portion of said redundancy signals along a channel not in said first plurality of channels and means for transmitting a second portion of said redundancy sIgnals as one signal in each of said first plurality of channels; and said calculating means establishing an orthogonal symmetry between said data signals and said second portion of said redundancy signals in each said signal set.

Claim 67

Dependent Claim 147 words

An error correction signal generating system for a multichannel digital transfer system, a first plurality of said channels transferring data representing digital signals, the improvement including in combination: means grouping data representing digital signals along each channel in signal groups having a number of signals equal to a number less than said first plurality; means associating all groups in said channel together as a multichannel signal set; means calculating check bit redundancy signals for all signals in one signal set; means for transmitting a first portion of said redundancy signals along a channel not in said first plurality of channels and means for transmitting a second portion of said redundancy sIgnals as one signal in each of said first plurality of channels; and said calculating means establishing an orthogonal symmetry between said data signals and said second portion of said redundancy signals in each said signal set.

Claim 68

Dependent Claim 244 words

A signal transfer system having error detection and correction capabilities, including in combination: a signal transfer apparatus having a given error mode; data signal means connected to said apparatus for exchanging data signals therewith; first means interposed between said apparatus and said data signal means for selecting a given number of said data signals and including means grouping said selected data signals into a plurality of channel bytes to form an error correcting signal set; error signal means in said first means receiving said data signals as cross-channel signal bytes, such cross-channel bytes having one data signal from each said channel bytes in accordance with a rectangular array of signals having one more signal along one dimension of said array than another dimension, redundancy means in said error signal means generating a redundancy signal byte having a number of check bit signals equal to the number of signals along said one dimension and operating on said signals as a square signal array with said redundancy signal byte in said array being parallel to said another dimension, means in said redundancy means relating each of said check bit signals to a unique group of said data signals such that all related signals (each check bit signal and its associated unique group of said data signals) exhibit orthogonal symmetry about a predetermined diagonal of said square array; and means in said first means exchanging a redundancy signal byte between said error signal means and said apparatus.

Claim 69

Dependent Claim 244 words

A signal transfer system having error detection and correction capabilities, including in combination: a signal transfer apparatus having a given error mode; data signal means connected to said apparatus for exchanging data signals therewith; first means interposed between said apparatus and said data signal means for selecting a given number of said data signals and including means grouping said selected data signals into a plurality of channel bytes to form an error correcting signal set; error signal means in said first means receiving said data signals as cross-channel signal bytes, such cross-channel bytes having one data signal from each said channel bytes in accordance with a rectangular array of signals having one more signal along one dimension of said array than another dimension, redundancy means in said error signal means generating a redundancy signal byte having a number of check bit signals equal to the number of signals along said one dimension and operating on said signals as a square signal array with said redundancy signal byte in said array being parallel to said another dimension, means in said redundancy means relating each of said check bit signals to a unique group of said data signals such that all related signals (each check bit signal and its associated unique group of said data signals) exhibit orthogonal symmetry about a predetermined diagonal of said square array; and means in said first means exchanging a redundancy signal byte between said error signal means and said apparatus.

Claim 70

Dependent Claim 67 words

The system set forth in claim 31 further including second error signal means in said first means for each signal set independently generating a separate second check bit signal on all signals in each said cross-channel bytes, plus a second check bit signal on said redundancy byte; and means exchanging all said second check bit signals between said signal transfer apparatus and said second error signal means.

Claim 71

Dependent Claim 78 words

The system set forth in claim 32 including error correction means receiving said data signals, said redundancy byte, and all said second check bit signals and for each said signal set for combining same to generate signals pointing to at least one of said bytes as being in error, if in error, and error pattern means selecting said redundancy byte exchanged with said signal transfer apparatus to indicate which bits of said byte in error are in error.

Claim 72

Independent Claim 150 words

The method of arranging data signals and generating check redundancy signals in connection with transferring digital data signals, including the steps of: dividing said digital data signals into successive signal sets, dividing each said signal set into a given plurality of channel bytes, the number of said digital data signals in each channel byte being one less than said given plurality; generating a first check redundancy signal byte having a number of signals equal to said given plurality and based upon a given error correcting polynomial of the irreducible type; generating a second check redundancy signal byte to have said given plurality of byte check bit signal portions, selecting signals from each said channel bytes and said first check redundancy signal byte to generate said check bit signal portions, respectively; and transferring said signal set and said first and second check redundancy signal bytes as a set of digital signals.

Claim 73

Independent Claim 150 words

The method of arranging data signals and generating check redundancy signals in connection with transferring digital data signals, including the steps of: dividing said digital data signals into successive signal sets, dividing each said signal set into a given plurality of channel bytes, the number of said digital data signals in each channel byte being one less than said given plurality; generating a first check redundancy signal byte having a number of signals equal to said given plurality and based upon a given error correcting polynomial of the irreducible type; generating a second check redundancy signal byte to have said given plurality of byte check bit signal portions, selecting signals from each said channel bytes and said first check redundancy signal byte to generate said check bit signal portions, respectively; and transferring said signal set and said first and second check redundancy signal bytes as a set of digital signals.

Claim 74

Dependent Claim 77 words

The method set forth in claim 34 further including the steps of: taking transferred signals and generating new first and second check redundancy signal bytes therefrom; and combining transferred first and second check redundancy signal bytes with said new first and second check redundancy signal bytes to generate pointer signals pointing to bytes in erroR and error pattern signals pointing to individual transferred data signals in said bytes in error for enabling correction of said individual signals.

Claim 75

Dependent Claim 57 words

The method set forth in claim 35 further including the steps of evaluating signal transfer and pointing to bytes possibly being in error based upon such evaluation; and selectively modifying said combining of said check redundancy signal bytes in accordance with said error possibility pointing for correcting a greater number of signals than without such error pointing.

Claim 76

Independent Claim 112 words

The method of preparing digital signals for recording such digital signals comprising the steps of: selecting a set of digital signals to be recorded, dividing said set into a given number less one of channel bytes, each channel byte having said given number of digital signals; generating a check byte of said given number of signals in an orthogonal symmetrical manner for each digital data signal set; independently generating a second check byte having an independent portion for groups of signals having one signal from each said channel byte and one portion for said check byte; and recording all signals of one set including said check bytes as a separate record entity.

Claim 77

Independent Claim 112 words

The method of preparing digital signals for recording such digital signals comprising the steps of: selecting a set of digital signals to be recorded, dividing said set into a given number less one of channel bytes, each channel byte having said given number of digital signals; generating a check byte of said given number of signals in an orthogonal symmetrical manner for each digital data signal set; independently generating a second check byte having an independent portion for groups of signals having one signal from each said channel byte and one portion for said check byte; and recording all signals of one set including said check bytes as a separate record entity.

Claim 78

Independent Claim 173 words

The method of reading correcting errors in digital signals read from a record member having recorded digital signals arranged in sets, each set having a predetermined number of digital data signals, a first redundancy signal subset exhibiting orthogonal symmetry with said digital signals in said set and a second redundancy signal subset in said set not exhibiting said orthogonal symmetry with said digital data signals but exhibiting a second error correcting characteristic, reading said signals from said record member, the method including the steps of: generating new first and second redundancy signals from digital data signals read from said record member, such new redundancy signals matching recorded redundancy signals in an error-free condition; comparing said new first and second redundancy signals with first and second redundancy signals read from said record member and generating an error location signal from said comparison showing that such error, if any, is in a given group of signals and error pattern signals showing which signals in such group are in error; and changing the signals in error.

Claim 79

Independent Claim 173 words

The method of reading correcting errors in digital signals read from a record member having recorded digital signals arranged in sets, each set having a predetermined number of digital data signals, a first redundancy signal subset exhibiting orthogonal symmetry with said digital signals in said set and a second redundancy signal subset in said set not exhibiting said orthogonal symmetry with said digital data signals but exhibiting a second error correcting characteristic, reading said signals from said record member, the method including the steps of: generating new first and second redundancy signals from digital data signals read from said record member, such new redundancy signals matching recorded redundancy signals in an error-free condition; comparing said new first and second redundancy signals with first and second redundancy signals read from said record member and generating an error location signal from said comparison showing that such error, if any, is in a given group of signals and error pattern signals showing which signals in such group are in error; and changing the signals in error.

Claim 80

Independent Claim 27 words

The method of preparing digital data signals for recording in a block of such signals in a multitrack record member, the method improvement including the steps of:

Claim 81

Independent Claim 27 words

The method of preparing digital data signals for recording in a block of such signals in a multitrack record member, the method improvement including the steps of:

Claim 82

Dependent Claim 40 words

The method of claim 39 further including the steps of generating a parity signal for each cross-channel byte independent of said check cross-channel byte generating indicating parity on such check cross-channel byte and recording such parity signals in one channel.

Claim 83

Independent Claim 98 words

The method of correcting signals in error in a set of digital data signals, including the steps of: arranging the signals in a rectangular array of channel bytes along a first array dimension and cross-channel bytes along a second array dimension; generating a check byte redundancy by successive byte calculations along one array dimension; generating a first set of syndrome signals and error pattern signals from said redundancy and data signals along said one array dimension; and correcting errors by applying said error pattern signals to data signals in one byte extending along a second one array dimension.

Claim 84

Independent Claim 98 words

The method of correcting signals in error in a set of digital data signals, including the steps of: arranging the signals in a rectangular array of channel bytes along a first array dimension and cross-channel bytes along a second array dimension; generating a check byte redundancy by successive byte calculations along one array dimension; generating a first set of syndrome signals and error pattern signals from said redundancy and data signals along said one array dimension; and correcting errors by applying said error pattern signals to data signals in one byte extending along a second one array dimension.

Claim 85

Dependent Claim 83 words

The method set forth in claim 41 Further including the steps of: generating a second redundancy along said second one array dimension independently of said first redundancy but having a check portion base upon said first redundancy; based generating a second set of syndrome signals based upon said second redundancy and said data signals and said first redundancy, and a second set of error pattern signals; and simultaneously applying said error patterns to two bytes, respectively, extending along said second one array dimension.

Claim 86

Dependent Claim 92 words

The method set forth in claim 42 and practiced in part in a linear feedback shift apparatus, the method of arranging said signals into said array including loading said bytes along said one array dimension serially into said shift register while synchronously shifting same and feeding back in accordance with a selected irreducible polynomial; storing said loaded bytes fed to said shift register in a storage apparatus; and applying said error pattern signals serially to selected two signals in each said loaded bytes while synchronously transferring such bytes from said storage apparatus.

Claim 87

Dependent Claim 128 words

A code circuit for a multichannel signal processing apparatus which processes a given number of signals from each channel as a group of signals, a check character set of signals being included in said group of signals and having one signal in each said channels, a multichannel network realizing polynominal g(x) and receiving said given signals in seriatim from said apparatus, one signal at a time from each channel in parallel with one signal from others of said channels after generating a syndrome character representative of errors in said given signals; first means indicating a single channel in error, means responsive to said indication for applying said syndrome character to said channel in error as an error pattern for correcting said given signals in said channel in error.

Claim 88

Dependent Claim 128 words

A code circuit for a multichannel signal processing apparatus which processes a given number of signals from each channel as a group of signals, a check character set of signals being included in said group of signals and having one signal in each said channels, a multichannel network realizing polynominal g(x) and receiving said given signals in seriatim from said apparatus, one signal at a time from each channel in parallel with one signal from others of said channels after generating a syndrome character representative of errors in said given signals; first means indicating a single channel in error, means responsive to said indication for applying said syndrome character to said channel in error as an error pattern for correcting said given signals in said channel in error.

Claim 89

Dependent Claim 106 words

The circuit set forth in claim 44 further including a parity channel in said apparatus having a given number of parity signals associated with said group of signals, the improvement further including in combination: second means in said first means indicating two channels in error and means inhibiting said first means indications when two channels in error are indicated, and means receiving said parity signals and said given signals to generate a parity syndrome character, means responsive to said second means to apply said syndrome characters as error patterns to respective ones of said two channels in error for correcting signals in said channels in error.

Claim 90

Dependent Claim 138 words

Code circuits for multichannel signal apparatus, including in combination: a check character generator circuit means realizing polynominal g(x) and generating a check character based upon received signals from all channels and means supplying said check character with one signal in each of said channels, first circuit means supplying successive sets of signals in parallel to said generator circuit, second circuit means responsive to a given number of said successive sets of signals being supplied to activate transfer of said check character as a check set of signals interleaved among said sets, control means for repeatedly activating said circuit means to generate a train of signal sets in all channels including interleaved check sets, and receiver means responsive to said check sets and associated ones of said sets of signals to correct signals in any one of said channels.

Claim 91

Dependent Claim 138 words

Code circuits for multichannel signal apparatus, including in combination: a check character generator circuit means realizing polynominal g(x) and generating a check character based upon received signals from all channels and means supplying said check character with one signal in each of said channels, first circuit means supplying successive sets of signals in parallel to said generator circuit, second circuit means responsive to a given number of said successive sets of signals being supplied to activate transfer of said check character as a check set of signals interleaved among said sets, control means for repeatedly activating said circuit means to generate a train of signal sets in all channels including interleaved check sets, and receiver means responsive to said check sets and associated ones of said sets of signals to correct signals in any one of said channels.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1978-02-24	1978-08-26	1979-02-25	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1982-02-24	1982-08-26	1983-02-25	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1986-02-24	1986-08-26	1987-02-25	$7700.00	Window Closed / Lapsed

Plural channel error correcting apparatus and methods

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