Patent US5230045A successfully refreshed from Google Patents.
US5230045A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple address space system including address translator for receiving virtual addresses from bus and providing real addresses on the bus
Assignee: Xerox Corp
•
Filing: 1992-04-07
•
Granted: 1993-07-20
•
Expires: 2012-04-07
Abstract
Abstract Virtual addresses from multiple address spaces are translated to real addresses in main memory by generating for each virtual address an address space identifier (AID) identifying its address space. Then, the virtual address and its AID are used to obtain the real address. The address spaces include a shared address space, from which the processor can provide a virtual address at any time, as well as switched address spaces, from one of which the processor can provide a virtual address at a given time. If the processor's local cache does not have data for the virtual address and cannot translate the virtual address to a real address, the local cache provides the virtual address on a bus. A dedicated VLSI map cache is connected for receiving virtual addresses from the bus and for providing real addresses on the bus. The bus is also connected for providing real addresses to access memory. The map cache, which can handle address translation for multiple processors connected to the bus, translates by keeping the most recently accessed mapping entries, each of which associates a virtual address and its AID with a real address. If the virtual address is from the shared address space, the map cache uses the shared AID, but if not, the map cache uses the current switched AID for the processor providing the virtual address.
Inventors
- 👤 Pradeep S. Sindhu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
221 words
A system comprising: a memory accessible with any of a set of real addresses; a plurality of processors, each of the plurality of processors requesting access to the memory by providing virtual addresses from a set of virtual addresses; each of the plurality of processors providing virtual addresses in one of a plurality of address spaces; a bus connected for receiving virtual addresses provided by each of the plurality of processors and for providing any of the set of real addresses to access the memory; each virtual address received by the bus being from the set of virtual addresses; and an address translator for translating virtual addresses provided by each of the plurality of processors to respective real addresses from the set of real addresses, the address translator being connected for receiving virtual addresses provided by each of the plurality of processors from the bus and for providing, for each virtual address, the respective real address on the bus; each virtual address received by the address translator being from the set of virtual addresses; the address translator comprising circuitry for obtaining, for a received virtual address, an address space identifier identifying one of the plurality of address spaces and for using the address space identifier and the received virtual address to obtain a respective real address for the received virtual address.
Claim 2
Independent Claim
221 words
A system comprising: a memory accessible with any of a set of real addresses; a plurality of processors, each of the plurality of processors requesting access to the memory by providing virtual addresses from a set of virtual addresses; each of the plurality of processors providing virtual addresses in one of a plurality of address spaces; a bus connected for receiving virtual addresses provided by each of the plurality of processors and for providing any of the set of real addresses to access the memory; each virtual address received by the bus being from the set of virtual addresses; and an address translator for translating virtual addresses provided by each of the plurality of processors to respective real addresses from the set of real addresses, the address translator being connected for receiving virtual addresses provided by each of the plurality of processors from the bus and for providing, for each virtual address, the respective real address on the bus; each virtual address received by the address translator being from the set of virtual addresses; the address translator comprising circuitry for obtaining, for a received virtual address, an address space identifier identifying one of the plurality of address spaces and for using the address space identifier and the received virtual address to obtain a respective real address for the received virtual address.
Claim 3
Dependent Claim
96 words
The system of claim 1, further comprising, for each of the plurality of processors, a respective cache connected between the processor and the bus; the cache storing respective data for each of a subset of the set of virtual addresses; the cache receiving the virtual address from the processor and providing the respective data in response to the virtual address if the virtual address is in the subset of virtual addresses; the cache further determining whether to provide the virtual address on the bus if the virtual address is not in the subset of virtual addresses.
Claim 4
Dependent Claim
36 words
The system of claim 2 in which the cache further receives the respective real address provided by the address translator from the bus and provides the respective real address on the bus to access the memory.
Claim 5
Independent Claim
316 words
A system comprising: a memory accessible with any of a set of real addresses; a plurality of processors, each of the plurality of processors requesting access to the memory by providing virtual addresses from a set of virtual addresses; each of the processors providing virtual addresses in one of a plurality of address spaces; a bus connected for receiving virtual addresses provided by each of the plurality of processors and for providing any of the set of real addresses to access the memory; each virtual address received by the bus being from the set of virtual addresses; for each of the plurality of processors, a respective cache connected between the processor and the bus; the cache storing respective data for each of a subset of the set of virtual addresses; the cache receiving the virtual address from the processor and providing the respective data in response to the virtual address if the virtual address is in the subset of virtual addresses; the cache further determining whether to provide the virtual address on the bus if the virtual address is not in the subset of virtual addresses; and an address translator for translating virtual addresses provided by the respective cache of each of the plurality of processors to respective real addresses from the set of real addresses, the address translator being connected for receiving virtual addresses provided by the respective cache of each of the plurality of processors from the bus and for providing, for each virtual address, the respective real address on the bus; each virtual address received by the address translator being from the set of virtual addresses; the address translator comprising circuitry for obtaining, for a received virtual address, an address space identifier identifying one of the plurality of address spaces and for using the address space identifier and the received virtual address to obtain a respective real address for the received virtual address.
Claim 6
Independent Claim
316 words
A system comprising: a memory accessible with any of a set of real addresses; a plurality of processors, each of the plurality of processors requesting access to the memory by providing virtual addresses from a set of virtual addresses; each of the processors providing virtual addresses in one of a plurality of address spaces; a bus connected for receiving virtual addresses provided by each of the plurality of processors and for providing any of the set of real addresses to access the memory; each virtual address received by the bus being from the set of virtual addresses; for each of the plurality of processors, a respective cache connected between the processor and the bus; the cache storing respective data for each of a subset of the set of virtual addresses; the cache receiving the virtual address from the processor and providing the respective data in response to the virtual address if the virtual address is in the subset of virtual addresses; the cache further determining whether to provide the virtual address on the bus if the virtual address is not in the subset of virtual addresses; and an address translator for translating virtual addresses provided by the respective cache of each of the plurality of processors to respective real addresses from the set of real addresses, the address translator being connected for receiving virtual addresses provided by the respective cache of each of the plurality of processors from the bus and for providing, for each virtual address, the respective real address on the bus; each virtual address received by the address translator being from the set of virtual addresses; the address translator comprising circuitry for obtaining, for a received virtual address, an address space identifier identifying one of the plurality of address spaces and for using the address space identifier and the received virtual address to obtain a respective real address for the received virtual address.
Claim 7
Independent Claim
300 words
A system comprising: a memory accessible with any of a set of real addresses; a plurality of processors, each of the plurality of processors requesting access to the memory by providing virtual addresses from a set of virtual addresses; each of the plurality of processors providing virtual addresses in one of a plurality of address spaces; a bus connected for receiving virtual addresses provided by each of the plurality of processors and for providing any of the set of real addresses to access the memory; each virtual address received by the bus being from the set of virtual addresses; and an address translator for translating virtual addresses provided by each of the plurality of processors to respective real addresses from the set of real addresses, the address translator being connected for receiving virtual addresses provided by each of the plurality of processors from the bus and for providing, for each virtual address, the respective real address on the bus; each virtual address received by the address translator being from the set of virtual addresses; the address translator comprising circuitry for obtaining, for a received virtual address, an address space identifier identifying one of the plurality of address spaces and for using the address space identifier and the received virtual address to obtain a respective real address for the received virtual address; the memory including a paged area and a map table with a plurality of entries, each map table entry associating a respective one of the set of virtual addresses with a respective one of the set of real addresses that accesses a page in the paged area; the address translator comprising a map cache with a plurality of cache entries, the plurality of cache entries including data indicating information from a subset of the plurality of map table entries.
Claim 8
Independent Claim
300 words
A system comprising: a memory accessible with any of a set of real addresses; a plurality of processors, each of the plurality of processors requesting access to the memory by providing virtual addresses from a set of virtual addresses; each of the plurality of processors providing virtual addresses in one of a plurality of address spaces; a bus connected for receiving virtual addresses provided by each of the plurality of processors and for providing any of the set of real addresses to access the memory; each virtual address received by the bus being from the set of virtual addresses; and an address translator for translating virtual addresses provided by each of the plurality of processors to respective real addresses from the set of real addresses, the address translator being connected for receiving virtual addresses provided by each of the plurality of processors from the bus and for providing, for each virtual address, the respective real address on the bus; each virtual address received by the address translator being from the set of virtual addresses; the address translator comprising circuitry for obtaining, for a received virtual address, an address space identifier identifying one of the plurality of address spaces and for using the address space identifier and the received virtual address to obtain a respective real address for the received virtual address; the memory including a paged area and a map table with a plurality of entries, each map table entry associating a respective one of the set of virtual addresses with a respective one of the set of real addresses that accesses a page in the paged area; the address translator comprising a map cache with a plurality of cache entries, the plurality of cache entries including data indicating information from a subset of the plurality of map table entries.
Claim 9
Dependent Claim
84 words
The system of claim 5 in which each map table entry and each map cache entry further associates the respective virtual address and a respective address space identifier with the respective real address; upon receiving a virtual address from one of the plurality of processors, the circuitry in the address translator obtaining an address space identifier identifying one of the plurality of address spaces and using the address space identifier in translating the virtual address provided by the processor to the respective real address.
Claim 10
Dependent Claim
68 words
The system of claim 5 in which the address translator further provides a signal indicating a map cache miss if a virtual address provided by one of the plurality of processors is not associated with the respective real address by any of the map cache entries; the memory further including software for servicing a map cache miss, the software being executed in response to the map cache miss.
Claim 11
Dependent Claim
35 words
The system of claim 7 in which the one of the plurality of processors that provided the virtual address responds to the map cache miss by executing the software for servicing a map cache miss.
Claim 12
Dependent Claim
35 words
The system of claim 7 in which the software for servicing a map cache miss, when executed, loads an entry including data indicating information from one of the map table entries into the map cache.
Claim 13
Dependent Claim
14 words
The system of claim 9 in which the map cache is a pure cache.
References Cited (Backward Citations)
US4145738A
Cited
US4481573A
Cited
US4473878A
Cited
US4495575A
Cited
US4654777A
Cited
US4513371A
Cited
US4774653A
Cited
US4694395A
Cited
US5029072A
Cited
US4727486A
Cited
US5123101A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-19 | 1997-01-18 | 1997-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-19 | 2001-01-18 | 2001-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-19 | 2005-01-18 | 2005-07-20 | $7700.00 | Window Closed / Lapsed |