Method and apparatus for controlling simultaneous switching output noise in boundary scan paths

Claim 2

An integrated circuit comprising: a plurality of output pads, each output pad including a conductive area to which other devices not included on the integrated circuit may be electrically connected to the integrated circuit for the purpose of receiving output from the integrated circuit; an output holding register, including a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; a clock line on which a clock signal is placed, the clock line being directly coupled to a first clock input on a first flip-flop; and, logic circuitry connected between the first clock input on the first flip-flop and a second clock input on a flip-flop, the logic circuitry introducing propagation delay in the clock signal before the clock signal reaches the second clock input, the propagation delay including propagation delay through the first flip-flop.

Claim 3

An integrated circuit as in claim 1 wherein the logic circuitry is a buffer.

Claim 4

An integrated circuit comprising: a plurality of output pads, each output pad including a conductive area to which other devices not included on the integrated circuit may be electrically connected to the integrated circuit for the purpose of receiving output from the integrated circuit; an output holding register, including a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; a clock line on which a clock signal is placed, the clock line being directly coupled to a first clock input on a first flip-flop; and, logic circuitry connected between the first clock input on the first flip-flop and a second clock input on a flip-flop, the logic circuitry introducing propagation delay in the clock signal before the clock signal reaches the second clock input, wherein the logic circuitry comprises a logical EXCLUSIVE NOR gate having a first input coupled to a first data output of the first flip-flop and having a second input coupled to a first data input of the first flip-flop, and a logical AND gate having a first input connected to an output of the logical EXCLUSIVE NOR gate, having a second input connected to the first clock input on the first flip-flop, and having an output connected to the second clock input on the second flip-flop.

Claim 5

An integrated circuit comprising: a plurality of output pads, each output pad including a conductive area to which other devices not included on the integrated circuit may be electrically connected to the integrated circuit for the purpose of receiving output from the integrated circuit; an output holding register, including a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; a clock line on which a clock signal is placed, the clock line being directly coupled to a first clock input on a first flip-flop; and, logic circuitry connected between the first clock input on the first flip-flop and a second clock input on a flip-flop, the logic circuitry introducing propagation delay in the clock signal before the clock signal reaches the second clock input, wherein the logic circuitry comprises a logical EXCLUSIVE NOR gate having a first input coupled to a first data output of the first flip-flop and having a second input coupled to a first data input of the first flip-flop, and a logical AND gate having a first input connected to an output of the logical EXCLUSIVE NOR gate, having a second input connected to the first clock input on the first flip-flop, and having an output connected to the second clock input on the second flip-flop.

Claim 6

An integrated circuit comprising: a plurality of output pads, each output pad including a conductive area to which other devices not included on the integrated circuit may be electrically connected to the integrated circuit for the purpose of receiving output from the integrated circuit; an output holding register, including a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; a clock line on which a clock signal is placed, the clock line being directly coupled to a first clock input on a first flip-flop; and, logic circuitry connected between the first clock input on the first flip-flop and a second clock input on a flip-flop, the logic circuitry introducing propagation delay in the clock signal before the clock signal reaches the second clock input; wherein a tri-state driver is coupled between a first data output of the first flip-flop and a first output pad and wherein the logic circuitry comprises a first input buffer having an input coupled to an output of the tri-state driver, a logical EXCLUSIVE NOR gate having a first input coupled to an output of the first input buffer and having a second input coupled to a first data input of the first flip-flop, and, a logical AND gate having a first input connected to an output of the logical EXCLUSIVE NOR gate, having a second input connected to the first clock input on the first flip-flop, and having an output connected to the second clock input on the second flip-flop.

Claim 7

An integrated circuit comprising: a plurality of output pads, each output pad including a conductive area to which other devices not included on the integrated circuit may be electrically connected to the integrated circuit for the purpose of receiving output from the integrated circuit; an output holding register, including a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; a clock line on which a clock signal is placed, the clock line being directly coupled to a first clock input on a first flip-flop; and, logic circuitry connected between the first clock input on the first flip-flop and a second clock input on a flip-flop, the logic circuitry introducing propagation delay in the clock signal before the clock signal reaches the second clock input; wherein a tri-state driver is coupled between a first data output of the first flip-flop and a first output pad and wherein the logic circuitry comprises a first input buffer having an input coupled to an output of the tri-state driver, a logical EXCLUSIVE NOR gate having a first input coupled to an output of the first input buffer and having a second input coupled to a first data input of the first flip-flop, and, a logical AND gate having a first input connected to an output of the logical EXCLUSIVE NOR gate, having a second input connected to the first clock input on the first flip-flop, and having an output connected to the second clock input on the second flip-flop.

Claim 8

An integrated circuit as in claim 1 additionally comprising a serial shift register coupled to the data input of each flip-flop in the output holding register.

Claim 9

An integrated circuit comprising: a plurality of output pads, an output holding register, including a plurality of blocks of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad, all flip-flops within each block of flip-flops being connected to a common block flip-flop line; a clock line on which a clock signal is placed, the clock line being directly coupled to a first common block flip-flop line for a first block of flip-flops; and, logic circuitry connected between the first common block flip-flop line for the first block of flip-flops and a second common block flip-flop line for a second block of flip-flops, the logic circuitry introducing propagation delay in the clock signal before the clock signal reaches the second common block flip-flop line, the propagation delay including propagation delay through at least one flip-flop from the first block of flip-flops.

Claim 10

An integrated circuit comprising: a plurality of output pads, an output holding register, including a plurality of blocks of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad, all flip-flops within each block of flip-flops being connected to a common block flip-flop line; a clock line on which a clock signal is placed, the clock line being directly coupled to a first common block flip-flop line for a first block of flip-flops; and, logic circuitry connected between the first common block flip-flop line for the first block of flip-flops and a second common block flip-flop line for a second block of flip-flops, the logic circuitry introducing propagation delay in the clock signal before the clock signal reaches the second common block flip-flop line, the propagation delay including propagation delay through at least one flip-flop from the first block of flip-flops.

Claim 11

An integrated circuit as in claim 6 wherein the logic circuitry is a buffer.

Claim 12

An integrated circuit as in claim 6 wherein the logic circuitry comprises: for every flip-flop in the first block of flip-flops, a logical EXCLUSIVE NOR gate having a first input coupled to a data output of the flip-flop and having a second input coupled to a data input of the flip-flop; and, a logical AND gate having a first input coupled to the first common block flip-flop line and having additional inputs coupled to outputs of each of the logical EXCLUSIVE NOR gates, and having an output connected to the second common block flip-flop line.

Claim 13

An integrated circuit as in claim 6 additionally comprising a serial shift register coupled to the data input of each flip-flop in the output holding register.

Claim 14

In an integrated circuit, a method for limiting simultaneous switching output noise on a plurality of output pads, the method comprising the steps of: (a) providing, by the integrated circuit to other devices not included on the integrated circuit, output signals via output pads, each output pad including a conductive area by which the other devices may be electrically connected to the integrated circuit; (b) providing the output signals from the integrated circuit to the output pads via an output holding register wherein the output holding register includes a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; and, (c) introducing various amounts of propagation delay in a clock signal before the clock signal reaches the clock inputs of the flip-flops, the propagation delay being introduced by logic circuitry, including the substeps of (c,1) connecting a clock input of a first flip-flop directly to the clock signal, and (c,2) serially connecting the clock inputs of the flip-flops together, the serial connections being made through logic gates, the logic gates introducing propagation delay including propagation delay through a one of said plurality of flip-flops.

Claim 15

In an integrated circuit, a method for limiting simultaneous switching output noise on a plurality of output pads, the method comprising the steps of: (a) providing, by the integrated circuit to other devices not included on the integrated circuit, output signals via output pads, each output pad including a conductive area by which the other devices may be electrically connected to the integrated circuit; (b) providing the output signals from the integrated circuit to the output pads via an output holding register wherein the output holding register includes a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; and, (c) introducing various amounts of propagation delay in a clock signal before the clock signal reaches the clock inputs of the flip-flops, the propagation delay being introduced by logic circuitry, including the substeps of (c,1) connecting a clock input of a first flip-flop directly to the clock signal, and (c,2) serially connecting the clock inputs of the flip-flops together, the serial connections being made through logic gates, the logic gates introducing propagation delay including propagation delay through a one of said plurality of flip-flops.

Claim 16

In an integrated circuit, a method for limiting simultaneous switching output noise on a plurality of output pads, the method comprising the steps of: (a) providing, by the integrated circuit to other devices not included on the integrated circuit, output signals via output pads, each output pad including a conductive area by which the other devices may be electrically connected to the integrated circuit; (b) providing the output signals from the integrated circuit to the output pads via an output holding register wherein the output holding register includes a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; and, (c) introducing various amounts of propagation delay in a clock signal before the clock signal reaches the clock inputs of the flip-flops, the propagation delay being introduced by logic circuitry, including the substeps of (c.1) arranging the flip-flops in blocks so that within a block a clock input of each flip-flop is connected to a common block flip-flop line, (c.2) connecting a first common block flip-flop line of a first block of flip-flops directly to the clock signal, and (c.3) serially connecting the common block flip-flop lines together, the serial connections being made through logic gates, the logic gates introducing propagation delay including propagation delay through a flip-flop.

Claim 17

In an integrated circuit, a method for limiting simultaneous switching output noise on a plurality of output pads, the method comprising the steps of: (a) providing, by the integrated circuit to other devices not included on the integrated circuit, output signals via output pads, each output pad including a conductive area by which the other devices may be electrically connected to the integrated circuit; (b) providing the output signals from the integrated circuit to the output pads via an output holding register wherein the output holding register includes a plurality of flip-flops, each flip-flop having a clock input, a data input, and a data output coupled to an output pad; and, (c) introducing various amounts of propagation delay in a clock signal before the clock signal reaches the clock inputs of the flip-flops, the propagation delay being introduced by logic circuitry, including the substeps of (c.1) arranging the flip-flops in blocks so that within a block a clock input of each flip-flop is connected to a common block flip-flop line, (c.2) connecting a first common block flip-flop line of a first block of flip-flops directly to the clock signal, and (c.3) serially connecting the common block flip-flop lines together, the serial connections being made through logic gates, the logic gates introducing propagation delay including propagation delay through a flip-flop.