Semiconductor integrated circuit having means for suppressing a variation in a threshold level due to temperature variation

Claim 2

A semiconductor integrated circuit comprising: an input circuit having a CMOS inverter of first and second series-connected transistors having respective gates connected in common at a connection node, the input circuit receiving an input signal at the connection node and emitting an output signal, said input circuit having a threshold level which determines the level of the output signal of the input circuit with respect to the level of the input signal, the threshold level varying as a function of variations of the temperature of the CMOS inverter; an internal circuit receiving said output signal of said input circuit and a first power supply voltage; and power source means, coupled to said input circuit and having an output node and a constant current source connecting the output node to a reference node, for receiving the first power supply voltage and further receiving at the reference node a reference power supply voltage of a level different from the level of the first power supply voltage, for generating, at the output node, a second power supply voltage having a level which varies, independently of the input signal and within a range intermediate the respective levels of the first power supply voltage and the reference power supply voltage, as a function of temperature and for supplying the second power supply voltage to said input circuit, said input circuit responding to the variations in the level of the second power supply voltage to cancel variations in the threshold level due to temperature variations.

Claim 3

A semiconductor integrated circuit as claimed in claim 1, wherein said power source means comprises means for increasing the second power supply voltage as the temperature decreases and for decreasing the second power supply voltage as the temperature increases.

Claim 4

A semiconductor integrated circuit as claimed in claim 1, wherein said power source means comprises: a transistor having a collector receiving said first power supply voltage, an emitter connected to the output node at which said second power supply voltage is output, and a base; and temperature compensating means, responsive to the variations in temperature of the CMOS inverter and coupled to said transistor, for generating a base voltage and applying the base voltage to the base of said transistor so that the base voltage changes due to the temperature variations.

Claim 5

A semiconductor integrated circuit as claimed in claim 3, wherein said temperature compensating means comprises means for generating the base voltage so that the base voltage decreases as the temperature increases.

Claim 6

A semiconductor integrated circuit as claimed in claim 1, wherein said power source means comprises: first, second and third constant current sources, the third constant current source comprising the constant current source connecting the output node to the reference node; a first transistor having a collector receiving said first power supply voltage, a base and an emitter; a first constant-current source being connected between a base of said first transistor and said reference node set at the reference voltage, the level thereof being lower than the level of said first power supply voltage; a first resistor connected between the collector and base of said first transistor; a first diode having an anode connected to the emitter of said first transistor and a cathode; a second transistor having a base connected to the cathode of said first diode, a collector and an emitter connected through a resistive conductive path to the reference node; a second resistor coupled between the base of the second transistor and said reference node; a third transistor having a collector receiving said first supply voltage, a base connected to the collector of said second transistor, and an emitter connected to the output node at which said second power supply voltage is produced; a third resistor connected between the collector and the base of said third transistor; and the second constant-current source being connected between the base of said third transistor and said reference node.

Claim 7

A semiconductor integrated circuit as claimed in claim 5, wherein said power source means further comprises a second diode having an anode connected to the cathode of said first diode and a cathode connected to the base of said first transistor.

Claim 8

A semiconductor integrated circuit as claimed in claim 6, wherein said first, second and third constant-current sources have respective control terminals receiving a common control voltage which determines the amounts of constant currents respectively generated by said first, second and third constant-current sources.

Claim 9

A semiconductor integrated circuit as claimed in claim 1, further comprising an output circuit amplifying a signal from said internal circuit, said output circuit receiving said first power supply voltage.

Claim 10

A semiconductor integrated circuit comprising: an input circuit having a CMOS inverter and receiving an input signal and emitting an output signal, said input circuit having a threshold level which determines the level of the output signal of the input circuit with respect to the level of the input signal, the threshold level varying as a function of variations of the temperature of the CMOS inverter; an internal circuit receiving said output signal of said input circuit and a first power supply voltage; and power source means, coupled to said input circuit and receiving the first power supply voltage and a reference voltage of a level different from the level of the first power supply voltage, for generating a second power supply voltage having a level which varies, within a range intermediate the respective levels of the first power supply voltage and the reference voltage, as a function of temperature and for applying the second power supply voltage to said input circuit, said input circuit responding to the variation in level of the second power supply voltage to cancel variations in the threshold level due to temperature variations, wherein said power supply means further comprises: a first transistor having a collector receiving said first power supply voltage, a base and an emitter; a first constant-current source connected between the base of said first transistor and a reference a node set at the reference voltage, the level thereof being lower than the level of said first power supply voltage; a first resistor connected between the collector and base of said first transistor; a first diode having an anode connected to the emitter of said first transistor and a cathode; a second transistor having a base connected to the cathode of said first diode, a collector and an emitter connected through a resistive conductive path to the reference node; a second resistor coupled between the base of the second transistor and said reference node; a third transistor having a collector receiving said first supply voltage, a base connected to the collector of said second transistor, and an emitter at which said second power supply voltage is produced; a third resistor connected between the collector and the base of said third transistor; a second constant-current source connected between the base of said third transistor and said reference node; and a third constant-current source connected between the emitter of said third transistor and said reference node.

Claim 11

A semiconductor integrated circuit comprising: an input circuit having a CMOS inverter and receiving an input signal and emitting an output signal, said input circuit having a threshold level which determines the level of the output signal of the input circuit with respect to the level of the input signal, the threshold level varying as a function of variations of the temperature of the CMOS inverter; an internal circuit receiving said output signal of said input circuit and a first power supply voltage; and power source means, coupled to said input circuit and receiving the first power supply voltage and a reference voltage of a level different from the level of the first power supply voltage, for generating a second power supply voltage having a level which varies, within a range intermediate the respective levels of the first power supply voltage and the reference voltage, as a function of temperature and for applying the second power supply voltage to said input circuit, said input circuit responding to the variation in level of the second power supply voltage to cancel variations in the threshold level due to temperature variations, wherein said power supply means further comprises: a first transistor having a collector receiving said first power supply voltage, a base and an emitter; a first constant-current source connected between the base of said first transistor and a reference a node set at the reference voltage, the level thereof being lower than the level of said first power supply voltage; a first resistor connected between the collector and base of said first transistor; a first diode having an anode connected to the emitter of said first transistor and a cathode; a second transistor having a base connected to the cathode of said first diode, a collector and an emitter connected through a resistive conductive path to the reference node; a second resistor coupled between the base of the second transistor and said reference node; a third transistor having a collector receiving said first supply voltage, a base connected to the collector of said second transistor, and an emitter at which said second power supply voltage is produced; a third resistor connected between the collector and the base of said third transistor; a second constant-current source connected between the base of said third transistor and said reference node; and a third constant-current source connected between the emitter of said third transistor and said reference node.

Claim 12

A semiconductor integrated circuit as claimed in claim 9, wherein said power source means further comprises a second diode having an anode connected to the cathode of said first diode and a cathode connected to the base of said first transistor.

Claim 13

A semiconductor integrated circuit as claimed in claim 10, wherein said first, second and third constant-current sources have respective control terminals receiving a common control voltage which determines the amounts of constant currents respectively generated by said first, second and third constant-current sources.

Claim 14

A semiconductor integrated circuit comprising: an input circuit having a CMOS inverter and receiving an input signal and emitting an output signal, said input circuit having a threshold level which determines the level of the output signal of the input circuit with respect to the level of the input signal, the threshold level varying as a function of variations of the temperature of the CMOS inverter; an internal circuit receiving said output signal of said input circuit and a first power supply voltage; power source means, coupled to said input circuit and receiving the first power supply voltage and a reference voltage of a level different from the level of the first power supply voltage, for generating a second power supply voltage having a level which varies, within a range intermediate the respective levels of the first power supply voltage and the reference voltage, as a function of temperature and for applying the second power supply voltage to said input circuit, said input circuit responding to the variation in level of the second power supply voltage to cancel variations in the threshold level due to temperature variations; an output circuit amplifying a signal from said internal circuit, said output circuit receiving said first power supply voltage.

Claim 15

A semiconductor integrated circuit comprising: an input circuit having a CMOS inverter and receiving an input signal and emitting an output signal, said input circuit having a threshold level which determines the level of the output signal of the input circuit with respect to the level of the input signal, the threshold level varying as a function of variations of the temperature of the CMOS inverter; an internal circuit receiving said output signal of said input circuit and a first power supply voltage; power source means, coupled to said input circuit and receiving the first power supply voltage and a reference voltage of a level different from the level of the first power supply voltage, for generating a second power supply voltage having a level which varies, within a range intermediate the respective levels of the first power supply voltage and the reference voltage, as a function of temperature and for applying the second power supply voltage to said input circuit, said input circuit responding to the variation in level of the second power supply voltage to cancel variations in the threshold level due to temperature variations; an output circuit amplifying a signal from said internal circuit, said output circuit receiving said first power supply voltage.