BICMOS TTL input buffer

Claim 2

An input buffer comprising: a buffer input; an operational amplifier including an inverting input and a non-inverting input; a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input; a voltage source connected to said non-inverting input; a first stage inverter connected to said buffer input and including substantially identically sized field effect transistors as those of the threshold inverter, said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter.

Claim 3

An input buffer as recited in claim 1 wherein said operational amplifier further comprises a pair of emitter coupled bipolar transistors and a pair of field effect transistors, the collectors of said bipolar transistors being connected to an associated field effect transistor of said field effect transistor pair.

Claim 4

An input buffer as recited in claim 1 where said operational amplifier is configured as a unity gain voltage follower.

Claim 5

An input buffer comprising: a buffer input; an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower; a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input; a voltage source connected to said non-inverting input; a first stage inverter, connected to said buffer input, and including field effect transistors, the sizes of said first stage inverter's transistors being selected so that the gate to source voltage of a selected transistor from said first stage inverter is always below a predetermined voltage level, said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter.

Claim 6

An input buffer comprising: a buffer input; an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower; a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input; a voltage source connected to said non-inverting input; a first stage inverter, connected to said buffer input, and including field effect transistors, the sizes of said first stage inverter's transistors being selected so that the gate to source voltage of a selected transistor from said first stage inverter is always below a predetermined voltage level, said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter.

Claim 7

An input buffer as recited in claim 4 wherein said operational amplifier further comprises a pair of emitter coupled bipolar transistors and a pair of amplifier field effect transistors, said collectors of said emitter coupled bipolar transistors being connected to an associated field effect transistor of said amplifier field effect transistor pair.

Claim 8

An input buffer as recited in claim 4 which further includes a bipolar transistor and wherein said plurality of field effect transistors are a p-channel transistor and a n-channel transistor, said p and n-channel transistors including common gates and common drains, and said predetermined voltage level being substantially equal to a TTL logic level high voltage plus the threshold voltage of said p-channel transistor minus a TTl logic level low voltage.

Claim 9

An input buffer comprising: a buffer input; an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower; a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input; a voltage source connected to said non-inverting input; a first stage inverter connected to said buffer input and including substantially identically sized field effect transistors as the threshold inverter, said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter, the sizes of said field effect transistors of said first stage inverter and said threshold inverter being chosen such that the gate to source voltage of a selected transistor from said first stage inverter is always below a predetermined voltage level.

Claim 10

An input buffer comprising: a buffer input; an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower; a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input; a voltage source connected to said non-inverting input; a first stage inverter connected to said buffer input and including substantially identically sized field effect transistors as the threshold inverter, said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter, the sizes of said field effect transistors of said first stage inverter and said threshold inverter being chosen such that the gate to source voltage of a selected transistor from said first stage inverter is always below a predetermined voltage level.

Claim 11

An input buffer as recited in claim 7 wherein said operational amplifier further comprises a pair of emitter coupled bipolar transistors and a pair of field effect transistors, said collectors of said bipolar transistors being connected to an associated field effect transistor of said field effect transistor pair.

Claim 12

An input buffer as recited in claim 7 wherein the voltage source comprises a band-gap reference voltage circuit including: a first device including at least a first and second terminal wherein the bias of said first terminal controls a reference current through said second terminal; a current mirror connected to said second terminal of said first device, for mirroring through itself, the reference current through said second terminal; and a band-gap sub-circuit, connected to said current mirror, for providing a bias, determined by the mirror current, to said first terminal.

Claim 13

An input buffer as recited in claim 9 wherein said current mirror comprises a diode device for receiving a predetermined current from said first device, said diode device being connected to said second terminal of the latter and to a transistor which is connected to said band-gap sub-circuit.

Claim 14

An input buffer as recited in claim 10 wherein said diode device comprises a field effect transistor including its drain connected to its gate.

Claim 15

An input buffer as recited in claim 10 wherein said transistor which is connected to said band-gap sub-circuit is a field effect transistor.

Claim 16

An input buffer as recited in claim 9 wherein said band-gap sub-circuit comprises two bipolar transistors including a common base connection and a control transistor connected to the collectors of said bipolar transistors of said band-gap sub-circuit.

Claim 17

An input buffer as recited in claim 13 wherein one said bipolar transistors of said band-gap sub-circuit is configured as a diode.

Claim 18

An input buffer as recited in claim 9 which further includes start-up circuitry for initially turning on said band-gap reference voltage circuit.

Claim 19

An input buffer as recited in claim 15 wherein said start-up circuitry includes first and second field effect transistors including a common gate and being connected to a third field effect transistor.

Claim 20

An input buffer as recited in claim 15 wherein said start-up circuitry includes a plurality of bipolar transistors connected together.

Claim 21

An input buffer as recited in claim 9 which further includes a voltage regulator, connected to said band-gap sub-circuit, for maintaining a substantially constant voltage potential at said first terminal.

Claim 22

An input buffer as recited in claim 18 wherein said voltage regulator comprises a diode configured transistor connected to the collector of a fourth bipolar transistor.

Claim 23

An input buffer comprising: a buffer input; an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower; a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input; a voltage source connected to said non-inverting input; a first stage inverter connected to said buffer input and comprising a p-channel transistor and an n-channel transistor, said p and n-channel transistors including a common drain connection and a common gate, connection said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter, the sizes of said field effect transistors of said first stage inverter and said threshold inverter being chosen such that the source voltage of said p-channel transistor is below a voltage level corresponding to a TTL logic level high plus the threshold voltage of said p-channel transistor.

Claim 24

An input buffer comprising: a buffer input; an operational amplifier including an inverting input and a non-inverting input, said operational amplifier being configured as a unity gain voltage follower; a threshold inverter including a threshold inverter input, a threshold inverter output, and a plurality of field effect transistors, said threshold inverter's input being connected to its output and to said inverting input; a voltage source connected to said non-inverting input; a first stage inverter connected to said buffer input and comprising a p-channel transistor and an n-channel transistor, said p and n-channel transistors including a common drain connection and a common gate, connection said first stage inverter being connected to said threshold inverter so as to mirror selected voltages of said threshold inverter to said first stage inverter, the sizes of said field effect transistors of said first stage inverter and said threshold inverter being chosen such that the source voltage of said p-channel transistor is below a voltage level corresponding to a TTL logic level high plus the threshold voltage of said p-channel transistor.

Claim 25

An input buffer as recited in claim 20 wherein said operational amplifier further comprises a pair of emitter coupled bipolar transistors and a pair of field effect transistors, the collectors of said bipolar transistors being connected to an associated field effect transistor of said field effect transistor pair.

Claim 26

An input buffer as recited in claim 21 wherein the voltage source comprises a band-gap reference voltage circuit including: a first device including at least a first and second terminal wherein the bias of said first terminal controls a reference current through said second terminal; a current mirror connected to said second terminal of said first device, for mirroring through itself, the reference current through said second terminal; and a band-gap sub-circuit, connected to said current mirror, for providing a bias, determined by the mirror current, to said first terminal.

Claim 27

An input buffer as recited in claim 22 wherein said current mirror comprises a regulator diode device for receiving a predetermined current from said first device, said regulator diode device being connected to said second terminal of the latter and to a transistor which is connected to said band-gap sub-circuit.

Claim 28

An input buffer as recited in claim 23 wherein said regulator diode device comprises a field effect transistor including its drain connected to its gate.

Claim 29

An input buffer as recited in claim 23 wherein said transistor of said regulator diode device is a field effect transistor.

Claim 30

An input buffer as recited in claim 22 wherein said band-gap sub-circuit comprises two bipolar transistors including a common base and a control transistor connected to the collectors of said bipolar transistors of said band-gap sub-circuit.

Claim 31

An input buffer as recited in claim 26 wherein one said bipolar transistors of said band-gap sub-circuit is configured as a diode.

Claim 32

An input buffer as recited in claim 22 which further includes start-up circuitry operable for initially turning on said band-gap reference voltage circuit.

Claim 33

An input buffer as recited in claim 28 wherein said start-up circuitry includes first and second field effect transistors including a common gate and being connected to a third field effect transistor.

Claim 34

An input buffer as recited in claim 28 wherein said start-up circuitry includes a plurality of bipolar transistors connected together.

Claim 35

An input buffer as recited in claim 22 which further includes a voltage regulator, connected to said band-gap sub-circuit, for maintaining a substantially constant voltage potential at said first terminal.

Claim 36

An input buffer as recited in claim 31 wherein said voltage regulator comprises a diode configured transistor connected to the collector of a fourth bipolar transistor.